HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 40

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C EC2
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Name
INT_S2
*
Reading the INT_S1 or INT_S2 register resets all active read interrupts in the INT_S1 or INT_S2
register respectively. New interrupts may occur during read. These interrupts are reported at the
next read of INT_S1 or INT_S2.
All interrupt bits are reported regardless of the mask registers settings (INT_M1 and INT_M2).
The mask registers settings only influence the interrupt output condition.
The interrupt output goes inactive during the read of INT_S1 or INT_S2. If interrupts occur during
this read the interrupt line goes active immediately after the read is finished. So processors with
level or transition triggered interrupt inputs can be connected.
important!
Addr.
11h
Bits
7..6
1
2
3
4
5
0
r/w Function
r
r
r
r
r
r
r
TE/NT state machine interrupt status
'1'
timer interrupt status
'1'
processing/non processing transition interrupt status
'1'
GCI I-change interrupt
'1'
receiver ready (RxR) of monitor channel
'1'
USB interrupt
'1'
unused, '0'
state of state machine changed
timer is elapsed
The HFC-S USB has changed from processing to non
processing state.
a different I-value on GCI was detected
2 monitor bytes have been received
bit 0 of register 01h has been set to '1' by a USB vendor
request
Cologne
Chip
:e\i " !