HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 42

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C EC2
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Name
CON_HDLC
[FIFO#]
Addr.
FAh
Bits
3..2
7..5
1
4
0
r/w Function
w
w
w
w
w
inter frame fill
'0' write HDLC flags as inter frame fill (reset default)
'1' write all '1's as inter frame fill (must be set for D-channel)
HDLC mode/transparent mode select
'0' HDLC mode (reset default)
'1' transparent mode select
transparent mode interrupt frequency
select
'00'
'01'
'10'
'11'
must be '0'
select data flow for selected FIFO
B1-channel (FIFO0 and 1, see FIFO#):
bit 5: '0'
bit 6: '0'
bit 7: '0'
B2-channel (FIFO2 and 3, see FIFO#):
bit 5: '0'
bit 6: '0'
bit 7: '0'
D-channel and PCM (FIFO4 and 5, see FIFO#):
bit 5: '0'
bit 6: '0'
bit 7: '0'
E-channel and PCM (FIFO6 and 7, see FIFO#):
bit 5: '0'
bit 6: '0'
bit 7: '0'
CON_HDLC register bits[7:5] must be the same for
corresponding receive and transmit FIFOs.
'1'
'1'
'1'
'1'
'1'
'1'
'1'
'1'
'1'
'1'
'1'
'1'
every 8 bytes
every 16 bytes
every 32 bytes
every 64 bytes
destination
FIFO1
FIFO1
B1-S/T
B1-PCM
B1-PCM
B2-S/T
B2-PCM
B2-PCM
B1-S/T
FIFO3
FIFO3
B2-S/T
FIFO5
FIFO5
D-S/T
D-S/T
AUX1
AUX1
FIFO7
FIFO7
E-S/T
E-S/T
AUX2
AUX2
source
B1-S/T
B1-PCM
FIFO0
B1-PCM
FIFO0
B1-S/T
B2-S/T
B2-PCM
FIFO2
B2-PCM
FIFO2
B2-S/T
D-S/T
AUX1
FIFO4
AUX1
FIFO4
D-S/T
E-S/T
AUX2
FIFO6
AUX2
FIFO6
E-S/T
if bits 3..1 are '0000'
the FIFO is disabled
(reset default)
Cologne
Chip
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