HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 58

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C EC2
6.2.2 Auxiliary port read access
Timing diagram 4: Auxiliary port read access
*)
**)
%( _V ("
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
CLK
SETUP
ADWLOW
HOLD
INSETUP
AXRDLOW
INHOLD
D
TRI
RDCYCSU
RDCYCHD
configurable (see also: CIRM register bit description)
depending on the setting of bit 4 of the CIRM register
Clock Period (24.576 MHz)
Address Setup Time before /ADR_WR
/ADR_WR Low Time
Address Hold Time after /ADR_WR
Minimum Data In Setup Time before /AUX_RD
/AUX_RD Low Time
Data In Hold Time after /AUX_RD
Delay Time between CLKI
Time Data Floating after CLKI
Read Cycle Setup Time
Output Data Valid after Read Cycle
CHARACTERISTICS
and /ADR_WR or /AUX_RD
20 ns
2x t
MIN.
20 ns
0 ns
t
t
t
CLK
CLK
CLK
*)
CLK
**)
40.69 ns
Cologne
Chip
MAX.
10 ns
:e\i " !
5 ns