HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 5

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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Figures
Figure 1: HFC-S USB block diagram ........................................................................................................... 7
Figure 2: Pin Connection for Passive USB Mode ........................................................................................ 9
Figure 3: Pin Connection for Active USB Mode........................................................................................ 13
Figure 4: FIFO control bytes for receive FIFOs ......................................................................................... 30
Figure 5: FIFO control byte for transmit FIFOs ......................................................................................... 31
Figure 6: Function of CON_HDLC register bits 7..5 ................................................................................. 43
Figure 7: External receiver circuitry........................................................................................................... 63
Figure 8: External wake-up circuitry .......................................................................................................... 64
Figure 9: External transmitter circuitry ...................................................................................................... 65
Figure 10: Oscillator circuitry for USB clock ............................................................................................ 68
Figure 11: Oscillator circuitry for USB clock ............................................................................................ 68
Figure 12: Oscillator circuitry for S/T clock .............................................................................................. 69
Figure 13: EEPROM circuitry .................................................................................................................... 70
Figure 14: Circuitry to use USB configuration data from internal ROM................................................... 70
Figure 15: Auxiliary port circuitry.............................................................................................................. 71
Figure 16: Power supply from USB............................................................................................................ 72
Figure 17: USB connection......................................................................................................................... 72
Figure 18: Frame structure at reference point S and T ............................................................................... 75
Figure 19: Single channel GCI format........................................................................................................ 76
Figure 20: Clock synchronisation in NT-mode .......................................................................................... 77
Figure 21: Clock synchronisation in TE-mode ........................................................................................... 78
Figure 22: HFC-S USB package dimensions.............................................................................................. 79
Tables
Table 1: Setup packet parameters for register access ................................................................................. 17
Table 2: FIFO endpoints and transfer types................................................................................................ 29
Table 3: FIFO control bytes for receive FIFOs .......................................................................................... 30
Table 4: FIFO control byte for transmit FIFOs .......................................................................................... 31
Table 5: S/T transformer module part numbers and manufacturers ........................................................... 67
Table 6: Activation/deactivation layer 1 for finite state matrix for NT ..................................................... 73
Table 7: Activation/deactivation layer 1 for finite state matrix for TE...................................................... 74
Timing diagrams
Timing diagram 1: Register write access.................................................................................................... 55
Timing diagram 2: Register read access ..................................................................................................... 56
Timing diagram 3: Auxiliary port write access .......................................................................................... 57
Timing diagram 4: Auxiliary port read access............................................................................................ 58
Timing diagram 5: PCM/GCI/IOM2 timing ............................................................................................... 59
Timing diagram 6: EEPROM access .......................................................................................................... 62
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Cologne
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