HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 55

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C EC2
6
6.1
6.1.1 Register write access
Timing diagram 1: Register write access
t
:e\i " !
CLK
SYMBOL
t
t
t
t
t
t
t
t
SA
SAH
WR
WRDSU
WRDH
RDY
RDYH
CYCLE
*
If the same register as in the last register read/write access is accessed the register address write is
not required.
can be found in Timing diagram 3.
hint!
Timing characteristics
Microprocessor access
Address to /WR Low Setup Time
Address Hold Time after /WR High
Write Time
Write Data Setup Time to /WR High
Write Data Hold Time from /WR High
Delay Time from /RD or /WR Low to /WAIT Low
Delay Time from /RD High or /WR High to /WAIT High
End of Write Data Cycle to Start of Next Read/Write Data Cycle
Time
CHARACTERISTICS
6x t
MIN.
20ns
20ns
50ns
30ns
10ns
3ns
3ns
CLK
Cologne
Chip
MAX.
30ns
30ns
%% _V ("
–
–
–