HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 57

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C EC2
6.2
6.2.1 Auxiliary port write access
Timing diagram 3: Auxiliary port write access
*)
**)
:e\i " !
C L K I
P O RT _ D [7 :0 ]
/A D R _ W R
/A U X _ W R
SYMBOL
t
t
t
t
t
t
t
t
CLK
SETUP
ADWLOW
HOLD
OUTSETUP
AXWLOW
OUTHOLD
D
Auxiliary port access
configurable (see also: CIRM register bit description)
depending on the setting of bit 4 of the CIRM register data out can be valid until the next
auxiliary port write access is initiated
Clock Period (24.576 MHz)
Address Setup Time before /ADR_WR
/ADR_WR Low Time
Address Hold Time after /ADR_WR
Data Out Setup Time before /AUX_WR
/AUX_WR Low Time
Data Out Hold Time after /AUX_WR
Delay Time between CLKI
t
S E T U P
t
A D R O U T
C L K
t
t
A D W L O W
D
t
D
CHARACTERISTICS
t
H O L D
and /ADR_WR or /AUX_WR
t
O U T S E T U P
t
D
D ATA O U T
t
A X W R L O W
* * )
2x t
2x t
MIN.
t
t
t
CLK
CLK
CLK
*)
CLK
CLK
t
O U T H O L D
40.69 ns
**)
Cologne
Chip
MAX.
10 ns
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