HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 56

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C EC2
6.1.2 Register read access
Timing diagram 2: Register read access
%& _V ("
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
RD
RDD
RDDH
SA
SAH
WR
WRDSU
WRDH
RDY
RDYH
CYCLE
*
If the same register as in the last register read/write access is accessed the register address write is
not required.
hint!
Read Time
/RD Low to Read Data Out Time
/RD High to Data Buffer Turn Off Time
Address to /RD or /WR Low Setup Time
Address Hold Time after /RD or /WR High
Write Time
Write Data Setup Time to /WR High
Write Data Hold Time from /WR High
Delay Time from /RD or /WR Low to /WAIT Low
Delay Time from /RD High or /WR High to /WAIT High
End of Read Data Cycle to End of Next Read/Write Data Cycle
Time
CHARACTERISTICS
6x t
MIN.
20ns
30ns
10ns
50ns
20ns
50ns
3ns
2ns
3ns
3ns
CLK
Cologne
Chip
MAX.
:e\i " !
25ns
15ns
30ns
30ns
–
–
–