HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 59

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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6.3
Timing diagram 5: PCM/GCI/IOM2 timing
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F0IO starts one C4IO clock earlier if bit 3 in MST_MODE0 register is set. If this bit is set F0IO is
also awaited one C4IO clock cycle earlier.
If bit 0 (or bit 1) of the MST_MODE2 register is set to '1' a frame signal for OKI
generated on F1_A (or F1_B). The C2O clock on F1_A is not available if bit 0 of the
MST_MODE2 register is set.
If bit 0 (or bit 1) of the MST_MODE2 register is cleared to '0' F1_A (or F1_B) is a CODEC enable
signal with the same pulse shape and timing as the F0IO signal.
If bits 5..4 of MST_MODE0 are '11' F1_A is C2O clock.
PCM/GCI/IOM2 timing
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