HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 78

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C EC2
10.2
Figure 21: Clock synchronisation in TE-mode
The C4IO clock is adjusted in the 31th time slot at the GCI/IOM bus 1..4 times for one half clock cycle.
This can be reduced to one adjustment of a half clock cycle (see MST_MODE1 register). This is useful if
another HFC series ISDN controller is connected as slave in NT mode to the PCM bus.
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S /T - In te rfa c e
Clock synchronisation in TE-mode
C L K D E L
R e c e iv e
D P L L
C L K 1 92 k H z
F R A M E -
S Y N C
D iv id e r
8 k H z
÷ 4
A
B
D iv id e r S e le ct
D P L L
M S T -
2 4.5 7 6 M H z
1 63 8 4
C L K
8 19 2
4 09 6
k H z
D iv id e r S e le ct
D iv id e r
÷ 20 4 8
÷ 10 2 4
÷ 51 2
P C M In te rfa ce
1 63 8 4 kH z
8 19 2 k H z
4 09 6 k H z
Cologne
Chip
C 4 IO
8 k H z
F 0IO
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