MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 16

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Notes:
1.
2.
Pinout Summary
81, 88, 90,
122, 129,
97, 120,
Pin #
Static memory stores the received cells. RAM is used for reordering the cells
These signals are used to transfer data between the MT90221 and the local processor
131
153
152
74
76
54
72
71
70
68
69
77
External Memory Interface
Microprocessor Interface
RX PCM Interface
TX PCM Interface
Miscellaneous
PLL Interface
RX UTOPIA
No Connect
TX UTOPIA
Ground
Name
Reset
TRST
Test1
Test2
Test3
Test4
Power
TMS
TDO
TCK
TDI
Type
Total
NC
Clk
208
I/O
O JTAG Test Data Output. Note: TDO is tristated by TMS pin.
I
I
I
I
I
I
I
I
I
I
No Connect. Can be left unconnected.
System Clock (25 MHz nominal). In the MT90221, this clock is used for all
internal operations of the device.
Test1. This signal should be pulled up for normal operation.
System Reset. This is an active low input signal. It causes the device to enter the
initial state. The Clk signal must be active to reset the internal registers.
JTAG Test Clock. It should be pulled down if not used
JTAG Test Mode Select. TMS is sampled on the rising edge of TCK. TMS has an
internal pull- up resistor.
JTAG Test Data Input.
TAG Test Reset (active low). Should be asserted LOW on power-up and during
reset. Must be HIGH for JTAG boundary-scan operation. Note: This pin has an
internal pull-down.
Test2. It should be pulled down for normal operation.
Test3. It should be pulled down for normal operation.
Test4. It should be pulled up for normal operation. NOT 5V TOLERANT
Input
16
14
12
10
63
7
4
System Signals
Output
10
22
41
1
1
4
2
1
Description
I/O
24
8
8
8
N.C.
24
24
Power
25
25
MT90221
Ground
31
31
7