MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 35

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
4.2.1.2
In this option, the 24 bytes of serial voice/data
channels of the DS-1 use the first 24 consecutive
channels over the 32 ST-BUS channels. The
MT90221 tri-states the DSTo lines for the unused
channels (25 - 31). Refer to Table 9.
4.2.1.3
When the T1 ISDN modes are selected, channel 24
is not used to carry bytes from ATM cells. This byte is
not used in the receive direction. In the transmit
direction it is set to a high impedance state. The ST-
BUS mapping is identical as in the T1 (DS1) ’clear
channel’ set-up except for the last channel of the T1
(DS1) frame. This last channel is reserved for
signaling.
26
Bit Cells
at DSTx0-3
Serial Bit
Stream
TXSYNC
RXSYNC
TXCK
RXCK
ST-BUS
Bit Cells
(DSTx0-3)
Serial Bit
Stream
TXSYNC0-3
RXSYNC0-3
TXCK 0-3
RXCK 0-3
ST-BUS
Bit Cells
at DSTx0-3
Serial Bit
Stream
TXSYNC0-3
RXSYNC0-3
TXCK 0-3
RXCK 0-3
Detailed ST-BUS Grouped Mapping
(24 Consecutive Channels)
Detailed ST-BUS ISDN Mapping
(T1 ISDN Modes)
NOTE: The value N is 0, 4, 8, 12, 16, 20, 24 or 28 and corresponds to the unused channels.
Figure 10 - PCM Mode 2 and 6: ST-BUS Interface for T1 (Grouped Mapping)
Channel 31 bit 0
High Impedance
Figure 9 - PCM Mode 2 and 6: ST-BUS Interface for T1 (Spaced Mapping
Unused or
Chan. N-1 bit 0
Chan. 31 bit 0
Bit Cell
Bit Cell
Channel 0 bit 7
Bit Cell
High Impedance
High Impedance
Chan. N bit 7
Chan. 0 bit 7
Unused or
Unused or
Channel 0 bit 6
Bit Cell
...
...
...
...
...
...
...
...
4.2.2
The Zarlink ST-BUS has 32 channels, numbered 0 to
31. The PCM-30 payload is mapped to 30 of the 32
ST-BUS timeslots. Channels 0 and 16 are used for
framing and signaling information. See Figure 11
and Table 10.
In E1 PCM Modes 4 and 8, the Zarlink ST-BUS clock
value is 4.096 MHz. The frame pulse is 8 kHz and
should be as defined in Figure 11.
In PCM Mode 4, the TXCK and TXSYNC pins are
defined as inputs and are generated by external
circuitry. In the PCM Mode 8, the TXCK and
TXSYNC pins are defined as outputs. The source for
the TXCK is selected using TX PCM Link Control
register number 2 and can be any of the four RXCK
High Impedance
High Impedance
Chan. 0 bit 0
Chan. N bit 0
Unused or
Unused or
...
...
...
...
Mode 4 and 8: ST-BUS lnterface for E1
Channel 23 bit 0
Chan. N+1 bit 7
Chan. 1 bit 7
Bit Cell
Bit Cell
Bit Cell
Channel 24 bit 7
High Impedance
Unused or
...
...
...
...
...
...
...
...
...
...
...
...