MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 25

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
Only one set of values is defined for the four Cell
Delineation state machines. The status of the CD
state machine for each link is available in bits 0 and 1
of the RX Cell Delineation State register.
The ITU I.432 suggested values are: ALPHA = 7;
and DELTA = 6.
Loss of Cell Delineation (LCD) is detected by
counting the number of incorrect cells while in HUNT
state. The MT90221 provides an internal Loss Cell
Delineation register to set the threshold for this
count. A value of 360 in the LCD register would
correspond to 79 msec for E1 and 100 msec for T1
applications. The LCD state for each link is available
in bit 1 of the IRQ LinkStatus registers, and in bit 6
of the RX Link ID Number register.
The LCD status bit is reporting the current condition
of the Cell Delineation State Machine at the time it is
read and cannot not be programmed to generate an
interrupt when exiting the LCD condition. The
software has to poll the status bit to determine when
the condition is cleared.
Table 3 provides the time, in microseconds, for the
CD circuit to receive a full ATM cell from the T1 and
E1 frame payloads.
While the cell delineation state machine is in the
SYNC state, the verification circuit implements the
state machine shown in Figure 6.
In normal operation, the HEC verification state
machine remains in the ’correction’ state. Incoming
cells containing no HEC errors are passed to the
receive IMA block (RX IMA). Incoming single-bit
errors can be corrected if required by the application
16
(PRESYNC State)
Format
Correct HCS’s
Consecutive
E1
T1
DELTA
Table 3 - Cell Acquisition Time
Average Cell Acquisition Time ( s)
Accepted
Cell
Correction
276
221
HCS Single Bit Error Detected (corrected or dropped)
Figure 6 - SYNC State Block Diagram
ATM CELL DELINEATION SYNC STATE
HCS Multi-Bit Error Detected (cell discarded)
No HCS Errors Detected
(i.e., single bit error correction can be enabled or
disabled).
After correction (when enabled), the resulting ATM
cell is passed to the RX IMA block for IMA
sequencing control.
If a single or multi bit error occurs, the state machine
goes to the ’detection’ state. When a cell with a good
HEC is detected, the state machine returns to the
’correction’ state. The HEC calculation normally
includes the ATM FORUM polynomial (X
+ 1). The use of the polynomial can be disabled by
writing to bit 1 of the RX Link Control register.
3.2
The CD circuit can de-scramble the cell payload
field. The de-scrambling algorithm can be enabled or
disabled using bit 5 of the RX Link Control registers.
The MT90221 can be programmed, using the RX
Link Control registers, to discard received ATM cells
with HEC error.
HEC error correction is optional and can be enabled
by the CPU. When the option to correct an incoming
HEC value with 1 bit error is selected, the HEC is
corrected and the cell is not counted as a cell with a
bad HEC. If the option to remove the cells that are
received with a bad HEC is selected, then the
incoming cells are replaced by a Filler cell in IMA
mode. The cell is simply discarded when in UNI
mode. The counter is not incremented if the HEC
value is corrected, when the option is enabled.
Incoming Idle and Unassigned cells can be detected
and dropped automatically.
3.3
The block diagram at Figure 7 illustrates the
MT90221 IMA mode receive path. The receiver must
rearrange the incoming bit streams from N-links (1
N
4) into a single UTOPIA cell stream.
De-Scrambling and ATM Cell Filtering
ATM Receive Path in IMA Mode
Detection
Discarded
Cell
Incorrect HCS’s
Jump to HUNT
Consecutive
6
ALPHA
State
+ X
4
+ X
2