MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 51

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MT90221

Manufacturer Part Number
MT90221
Description
Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
Manufacturer
Zarlink Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT90221ALX04
Quantity:
20
MT90221
42
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
Bit #
7-4
1-0
7:5
4:0
3
2
1
0
a. Unassigned Cells have a fixed header corresponding to 00000000 00000000 00000000 0000xxx0.
b. Idle Cells have a fixed header corresponding to 00000000 00000000 00000000 00000001
7
6
5
4
3
2
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Reserved. Write all 0’s .
Enable UTOPIA PHY address of IMA Group 3. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 2. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 1. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 0. A 1 enables the PHY port Address.
Unused. Read all 0’s.
UTOPIA PHY Address of link N when in UNI (non-IMA) mode.
Reserved.
UTOPIA Input Reset. A 1 will reset the UTOPIA Input State Machine. All other user
programmable registers are not cleared. A 0 is used for normal operation.
Reserved. Write 0.
Unassigned Cell Filter. A 1 signifies that the Unassigned
will be discarded. The Unassigned/Idle cell counter is incremented for each cell
discarded.
Idle Cell Filter. A 1 signifies that the Idle
discarded. The Unassigned/Idle cell counter is incremented for each cell discarded.
ATM Forum Polynomial. A 1 disables the addition of the ATM Forum Polynomial
calculation on the HEC calculated as per I.432. A 0 means that the closest value is
included in the HEC value.
HEC Verification.
11: Enable HEC error correction if 1 bit is wrong, discard cell if more than 1 bit are wrong.
10: Discard cell if HEC is wrong, ho HEC correction.
01: Enable HEC error correction if 1 bit is wrong, no correction if more than 1 bit wrong,
cell is not discarded if HEC is wrong.
00: No verification of HEC.
00D
1 register to enable the IMA Groups. The TxClk signal must be active for correct
register operation
00
00E
correct register operation
00
040 - 043
register operation
00
1 register for all the UTOPIA Input ports. The TxClk signal must be active for
1 register per link in UNI mode. The RxClk signal must be active for correct
Table 15 - UTOPIA Input Group PHY Enable Register
Table 17 - UTOPIA Output Link Address Registers
Table 16 - Utopia Input Control Register
Description
Description
Description
b
cells coming from the ATM layer will be
a
cells coming from the ATM layer

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