MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 53

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
44
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
7-4
7-4
3
2
1
0
3
2
1
0
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Table 21 - RX UTOPIA IMA Group FIFO Overflow Enable Register
Reserved. Write 0 for normal operation.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link3.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 2.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 1.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 0.
Unused. Read all 0’s.
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Group 3.
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Group 2.
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Group 1.
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Group 0.
Table 22 - RX UTOPIA Link FIFO Overflow Enable Register
221
must be active for correct register operation
00
active for correct register operation
205
00
1 register to enable interrupts from the links in UNI mode. The RxClk signal
1 register to enable interrupts from IMA Groups. The RxClk signal must be
Description
Description