MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 46

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

6.3.2
Direct access registers can be written or read
directly by the microprocessor, without having to use
otherregisters. Upon a write access to the MT90221
internal registers, the data is stored in an internal
latch and transferred to the destination register
within 2.5 system clock cycles (100 nsec at 25 MHz).
No specific action is required if the microprocessor
provides at least 100 nsec (with Chip Select signal
inactive) between 2 consecutive write accesses or
between a write and a read back of the same
register. If the microprocessor is faster, then
consecutive accesses must be inhibited or wait
state(s) introduced (this option is available on most
MCUs).
6.3.3
Indirect access registers cannot be accessed directly
by the microprocessor. The value is transferred back
and forth using registers which hold a copy of the
information (data) and internal address of the
register. This is required to stabilize the read value.
Consider for example the transfer of a TX ICP cell
that requires almost 200 system clock cycles. A
dedicated ready bit which can optionally generate an
interrupt is implemented for this type of transfer.
Accessing any of the 24 bit counters provides
another example. A ready bit is implemented in the
Counter Transfer Command register when the
transfer is completed.
When accessing indirect registers specified by the
RX Delay Select or RX Load Values/Link Select
registers, the value in the indirect registers can be
read when the write to the selection register is
effectively done (i.e. 2.5 system clock cycles after
the write cycle is completed). There is no additional
delay required.
6.3.4
The status bits will remain set until cleared by a
specific write action from the microprocessor. Status
bits are cleared by overwriting a zero to the
corresponding position in the source register. Each
input status register has a related interrupt enable
register. When enabled, setting a bit in the interrupt
enable register causes an interrupt to occur in the
corresponding status register bit.
6.3.4.1
Some registers include a toggle bit. Toggle bits are
used to indicate a write action to any internal register
has taken place. Typically, this bit is toggled 2.5
system clock cycles after performing the write action.
To use the toggle bit, its state (either 0 or 1) must be
read (polled) and its state is changed (toggled) when
a write command is completed. This bit is particularly
Direct Access
Indirect Access
Clearing of Status Bits
Toggle Bit
useful when the processor clock is much faster than
the MT90221 system clock.
6.3.5
Access is provided to the External SRAM from the
microprocessor using a special test mode and test
registers (i.e., to assist in debugging or verification).
The test mode is enabled by writing to bit 7 of the
Test Mode Enable register, writing 0x10 to the RX
Delay Link Number register and by writing 0x29 to
the RX External SRAM Control register. Indirect
access is provided using the RX External SRAM
Read/Write Data register for the data to be written or
read and the RX SRAM External Address 0, 1 and
2 registers for the address of the SRAM location. The
write transfer command is issued using the RX
External SRAM Control register. Bit 7 of the RX
External SRAM Control is cleared (set to 0) and
then returned to 1 when the write action is
completed.
Please note that during normal operation, the
microprocessor access to the External SRAM should
be disabled. This is done by writing 0x00 to the RX
Delay Link Number register.
Test Modes
MT90221
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