MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 95

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
AC Electrical Characteristics
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25 C, V
86
PCM
Bit Cells
T1 (1.544 Mbps)
PCM
Bit Cells
E1 (2.048 Mbps)
TXSYNC0-3/
RXSYNC0-3
TXCK0-3/
RXCK0-3
TXSYNC0-3/
RXSYNC0-3
TXCK0-3/
RXCK0-3
10
1
2
3
4
5
6
7
8
9
TXCK/RXCK Clock period
for T1, 1.544 MHz mode
for E1, 2.048 MHz mode
TXCK/RXCK Clock Width High or
Low
for T1, 1.544 MHz mode
for E1, 2.048 MHz mode
Frame Pulse Setup
Frame Pulse hold
DSTi 0-3 Serial Input Setup
DSTi 0-3 Serial Input Hold
DSTo 0-3 Serial Output Delay
TXSYNC/RXSYNC Frame Pulse
delay after TXCK/RXCK active
border
TXSYNC when input (PCM Mode 5
& 7) is sampled at the end of the bit
period
TXSYNC when input (PCM Mode 5
& 7) is sampled at the end of the bit
period
Characteristic
DD
Channel 24
Channel 31
LSB Bit
LSB Bit
=3.3V, and for design aid only: not guaranteed and not subject to production testing
Figure 26 - Generic PCM Interface Timing Diagram
†
- Generic PCM Interface Mode
Channel 0
MSB Bit
Framing
(Frame Pulse Location)
t
Bit
Sym
t
t
t
t
FPSH
tcyc
t
t
t
t
SOD
FPSi
FPS
FPH
FPD
SIH
SIS
4W
25ns
10ns
Min
260
195
4
1
3
0
Positive Pulse
Negative Pulse
Channel 1
Channel 0
MSB Bit
Typ
648
488
Bit 2
‡
Max
t
t
25
25
cyc
cyc
.5
.5
Units
Channel 1
Channel 0
ns
ns
ns
ns
ns
ns
ns
ns
Bit 2
Bit 3
duty cycle 40 / 60%
CL = 150pF
CL = 150pF
Test Conditions
BIT Transmitted at
Rising Edge
BIT Sampled at
Falling Edge
BIT Transmitted at
Falling Edge
BIT Sampled at
Rising Edge