MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 34

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

In PCM Modes 1, 3, 5 and 7, polarity of clock and
synchronization signals (TXCK, TX SYNC, RXCK
and RX SYNC) can be set as either positive or
negative. In the ST-BUS mode 2, 4, 6 and 8, the
clock and frame pulse are fixed and must conform to
the ST-BUS specification.
The RXCK and RXSYNC pins are always defined as
inputs and are generated by external circuitry.
4.2.1
In PCM Mode 2 the TXCK and TXSYNC pins are
defined as Inputs and in PCM Mode 6, the TXCK and
TXSYNC are defined as outputs. The RXCK and
RXSYNC are always defined as input pins.
In T1 applications, a DS-1 frame is 193 bits long and
corresponds to 1 framing bit and 192 payload bits.
The 192 payload bits are divided as 24 channels or
time slots of 8 bits each.
The Zarlink ST-BUS has 32 channels numbered 0 to
31. Two different mapping schemes are selectable.
The spaced mapping scheme uses 3 of every 4
channels. The grouped scheme uses the first 24
channels. Refer to Table 8 for details of Spaced DS-1
mapping, Table 9 for Grouped DS1 mapping. All
unused channels are tri-state.
DS1 Time slots
Voice/Data Channels
(DSTi/o)
ST-BUS
DS1 Time slots
Voice/Data Channels
(DSTi/o)
ST-BUS
DS1 Time slots
Voice/Data Channels
(DSTi/o)
ST-BUS
DS1 Time slots
Voice/Data Channels
(DSTi/o)
ST-BUS
Mode 2 and 6: ST-BUS Interface for T1
Table 8 - T1Channel Mapping Using 3 Channels Every 4 Channels
Table 9 - T1 Channel Mapping Using 24 Consecutive Channels
0
1
6
1
0
1
7
1
6
x
x
-
-
1
1
1
3
1
7
2
1
1
8
1
7
2
2
1
4
1
8
3
2
1
9
1
8
3
3
1
5
1
9
4
3
2
0
1
9
4
2
0
5
4
2
1
2
0
x
x
-
-
4
5
1
6
2
1
6
5
2
2
2
1
The Zarlink ST-BUS clock value is 4.096 MHz. The
frame pulse is 8 kHz and should be as defined in
Figure 9 or Figure 10 (see Zarlink Application Note
MSAN-126).
In the PCM Mode 6, the TXCK and TXSYNC pins are
defined as outputs. The source for the TXCK is
selected using TX PCM Link Control register number
2 and can be any of the four RXCK or four external
REFCK clocks. As there is no PLL inside the
MT90221, the source frequency has to be a valid ST-
BUS Clock signal (i.e., 4.096 MHz). The TXSYNC
signal is generated by the MT90221 and meets the
ST-BUS format. It is not synchronized with any other
RXSYNC or TXSYNC signal.
4.2.1.1
DS1 (T1) links contain 24 bytes of serial voice/data
channels distributed over the 32 ST-BUS channels.
One mapping option uses 3 of every 4 channels. The
channels 0, 4, 8, 12, 16, 20, 24 and 28 of the ST-BUS
are not used. The MT90221 tri-states the DSTo lines
during the unused time-slots. See Figure 9.
5
6
1
7
2
2
7
6
2
3
2
2
6
7
1
8
2
3
8
7
2
4
2
3
Detailed ST-BUS Spaced Mapping
(3 of Every 4 Channels)
8
x
2
4
x
9
8
2
4
x
-
-
-
7
9
1
9
2
5
1
0
9
2
5
x
-
8
1
0
2
0
2
6
1
1
1
0
2
6
x
-
9
1
1
2
1
2
7
1
2
1
1
2
7
x
-
1
2
x
2
8
x
1
3
1
2
2
8
x
-
-
-
MT90221
1
0
1
3
2
2
2
9
1
4
1
3
2
9
x
-
1
1
1
4
2
3
3
0
1
5
1
4
3
0
x
-
1
2
1
5
2
4
3
1
1
6
1
5
3
1
x
-
25