MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 42

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

6.0 Support Blocks
6.1
The MT90221 includes 64 24-bit counters to provide
statistical information on the device’s operation. All
the counters are cleared by a hardware reset. A
maskable interrupt can be generated when the
counter overflows.
A predetermined value can also be loaded in a
counter. This feature can be used to generate an
interrupt after a specified number of cells is
processed. Counter values are incremented by 1 for
every event occurrence and, when the count goes to
all 1’s, will overflow (to all 0’s).
6.1.1
There are four counters associated with the each of
the 8 UTOPIA Inputs (from ATM layer to the
MT90221) for a total of 32 counters. These counters
record the following information:
•
•
•
•
6.1.2
There are four counters associated with the each of
the four transmit PCM links for a total of 16 Transmit
counters. These counters record the following
information and are active as soon as the RX PCM
port is enabled:
•
•
•
Device
the total number of cells received at the
UTOPIA Input I/F
the total number of Idle Cells received at the
UTOPIA Input I/F, removed or not
the total number of Unassigned Cells received
at the UTOPIA Input I/F, removed or not
the number of cells having a single or multiple
bit error in the HEC, removed or not but not
including the cells where the HEC is corrected
the total number of cells sent through the PCM
link
the total number of Idle/Filler cells sent through
the PCM link, with good or bad HEC
the total number of Stuff cells sent through the
PCM link
ATM
Layer
Counter Block
UTOPIA Input I/F counters
Transmit PCM I/F Counters
Figure 17 - ATM Mixed-Mode Interface to One MT90221
2 UTOPIA Ports
1 UTOPIA Port
(IMA Group #1)
(UNI)
(2 Links in UNI Mode)
(2 links)
•
6.1.3
There are four counters associated with each of the
four receive PCM links for a total of 16 Receive
counters. These counters record the following
information:
•
•
•
•
6.1.4
Accessing (READ) counters is a three step function.
First, the desired counter must be selected by writing
to the Counter Select Register. Second, the READ
command (’0x00x101’) is written to the Counter
Transfer Command register. This command causes
the current three byte count value to be copied from
the specified counter to the three byte-wide Counter
Bytes registers (note that this value is unchanged
until another counter read command is issued). And
third, the Counter Bytes registers are read to obtain
the three byte count value of the selected counter.
Pre-loading (WRITE) a counter is also a three step
function. First, the three byte, pre-load value, is
written to the three byte-wide Counter Bytes
registers. Second, the identification of the counter to
be pre-loaded is written to the Counter Select
Register.
(’0x00x001’) is written to the Counter transfer
Command register.
The IRQ enable bit of a counter is set, or reset, by
selecting the counter and writing to the appropriate
the total number of ICP cells sent through the
PCM link
the total number of cells received through the
PCM link or total number of Stuff events
received on the link (option selected in RX Link
Control registers)
the total number of Idle/Filler cells received
through the PCM link
the total number of ICP Cells with violation
received through the PCM link
the total number of cells with wrong HEC
received through the PCM link but not including
the cells where the HEC is corrected
Receive PCM I/F Counters
Access to the Counters
And
third,
the
WRITE
4
MT90221
Framer
command
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