MTC-20172-PC AMI Semiconductor, Inc., MTC-20172-PC Datasheet - Page 15

• Manufacturer Part Number: MTC-20172-PC
• Description: S Interface Circuit for ISDN (SIC)
• Manufacturer: AMI Semiconductor, Inc.

The SIC can be used in a point-to-point
and in a point to multipoint
configuration (including extended
passive bus). In the first configuration,
the length of the cable is limited to
aprox. 1.2 km (see fig.2.6).
In the bus configuration (point to
multipoint), up to 8 terminals may be
connected to the S
The terminals must be connected in a
range of 150 m. For the extended
passive bus, the terminals must be
clustered within a 25m range with a
maximum cable length of about 1 km.
To avoid bus mismatching when
multiple TEs are connected, the driver
stages present a high impedance
when they are not powered.
Fig. 2.6 : Point to Point Configuration
Fig. 2.7 : Point to Multipoint Configuration
V* GCI
TE/LTT
T
R
0
-interface (fig.2.7).
SIC
TE # 1
SIC
<150 m
T
R
Controlled access to the shared data
channels is realized within the SIC by
a D-channel access procedure. Each
terminal can be given a certain
priority for D access. Via the echo bit,
which is the reflection of the received
D channel at the NT, it is possible for
the terminal to detect the status of the
D-channel. In order to try to gain
access over the D-channel, a terminal
has to see 8 to 11 consecutive ones in
the echo-channel. The exact number
depends on the priority given to the
terminal. When several terminals try to
gain access at the same time,
collisions occur on the S-bus. The
terminal that transmitted "one" but
sees a “zero” in the echo channel
detects the collision and loses the D-
channel access.
MAX 8
<= 1.2 Km
TE # 8
SIC
5
T
R
T
R
T
R
TERMINATING RESISTOR
T
R
T
R
MTC-20172
Data Sheet & Reference Manual
Rev. 1.1 February 1997
The terminal that transmitted the
"zero" gains the access. When a
successful D-channel message is
transmitted, the priority is decreased
by 1 in order to guarantee fairness
with the other terminals. The status of
the D-channel of the TE/LTT is
available at a device pin, or at the 5th
bit position of the monitor byte. This
enables the control of the D-channel
by an external HDLC controller.
At the NT/LTS side, the echo bits of
several NTs can be combined in an
external common echo bus (wired
AND) in an NT-star configuration. At
the LTS side, the same external
common echo bus can be used to
share an external HDLC controller
between several LTS SICs.
SIC
NT/LTS
of 100 Ω
V* GCI
SIC
NT/LTS
V* GCI