MTC-20172-PC AMI Semiconductor, Inc., MTC-20172-PC Datasheet - Page 26

• Manufacturer Part Number: MTC-20172-PC
• Description: S Interface Circuit for ISDN (SIC)
• Manufacturer: AMI Semiconductor, Inc.

The M channel is a 64 kbit/s channel.
It has a byte oriented structure, and
the content is indicated and
acknowledged with the MR and MX
bits - the two last bits in the B1*
channel. The content of the channel is
used to write and read the internal
MTC-20172 SIC registers. Its use is
optional in the MTC-20172 SIC.
4.6.3 Power-down on GCI
For maximal power saving, the GCI
bus can be halted completely and
reactivated asynchronously from either
side of the bus.
Section 4.9 gives a general
description of the power-down
features of the MTC-20172 SIC.
Chapter 6 gives the detailed
behaviour.
4.7 GCI Clock-
In general, the downstream devices
are slaved to the upstream devices.
Upstream MTC-20172 SIC
(NT/LT-S):
A MTC-20172 SIC in the NT/LT-S
position is master of the S-bus, and
can sample the received (upstream) S-
bus frames with a receive clock at
exactly the transmitted frequency, but
with an unknown phase.
In the NT/LT-S mode the MTC-20172
SIC receives the GCI timing, and must
derive the 192 kHz S-bus bit-clock
from it. As the GCI timing is not
necessarily a multiple of 192 kHz, the
MTC-20172 SIC generates a 192 kHz
TX and RX clock from a crystal or from
a clock input at 7680 kHz (±100
Synchronization in
the ISDN
Environment
ppm). The 192 kHz clock is not a
pure division by 40 of the crystal
frequency, but is locked to the 8 kHz
frame signal of the GCI interface. This
is a DPLL action, where the 192 kHz
clock period can be adjusted by ± 1
1/40 every 250 µs. Note that jitter
on the 192 kbit S-bus signals is a
combination of the jitter on the 7680
kHz before the DPLL and the effects of
the DPLL locking to the GCI 8 kHz
frame.
The S-bus RX clock in fixed timing
(short passive bus) is derived from the
same crystal, with the same frequency
correction as the transmit clock but
with a phase offset. The corrections of
1/40 of a bit period are used in an
open loop mode here.
The S-bus RX clock in adaptive timing
(extended bus, point-to-point) is also
derived from the same crystal.
However, the receiver must optimize
the symbol sampling moment. This is
an extra phase correction, which
tracks wander and jitter of the
received data.
The receiver tracks the RX data by
locking on the F/L transitions.
Note: The timing stays identical for an
internal analog loop from TX to RX,
because then the MTC-20172 SIC
uses adaptive RX timing as well. Even
an external S-bus loop can be
applied, provided that the receiver
does NOT work with fixed RX timing.
Conclusion: in NT/LT-s, the MTC-20172
SIC has 3 different clocks, which are
locked in frequency, but with unknown
phase relation. Because the clocks are
derived via PLL and DPLL blocks, the
phase relation is not constant, but has
some jitter and wander.
Downstream MTC-20172 SIC
(TE):
In the TE mode, the timing is slaved to
the S-bus and the upstream network.
The MTC-20172 SIC generates a
192 kHz RX sampling clock from a
16
MTC-20172
Data Sheet & Reference Manual
Rev. 1.1 February 1997
crystal or from a clock input at 7680
kHz 100 ppm. This 192 kHz is
locked to the 4 kHz frame signal of
the S-bus. This DPLL action adjusts the
192 kHz clock period 1 1/40 every
250 µs.
The GCI clock and frame are
generated by the MTC-20172 SIC,
derived from the received S-bus
timing. The transmit clock is also in
fixed relation to the receive timing. To
correct for external delays, the phase
of the TX clock is adjustable, see
section 5.4.3.
Conclusion: in TE mode the MTC-
20172 SIC has all clocks locked to
the 192 kHz RX S-bus data, with a
fixed deterministic phase relation,
except when loops are applied as
explained below.
Downstream MTC-20172 SIC
(TE) in analog loop:
When the downstream MTC-20172
SIC is looped (analog internal loop,
not transparent) the linking and phase
relation of the different clocks is
completely different. The MTC-20172
SIC uses its local crystal as master
clock and derives the S-bus TX and RX
clock and GCI timing. The S-bus
transceiver behaves as an upstream
device. However, it monitors the RX
signals to activate if desired.
Moreover, the loop is not transparent,
i.e. no signal is sent to the actual S-bus.
Downstream MTC-20172 SIC
(LT-T):
In the LT-T, the S-bus and the GCI
timing are both enforced on the MTC-
20172 SIC. They are not necessarily
synchronized or even locked.
To allow the GCI clock to be
synchronized on the S-bus clock, the
MTC-20172 SIC has a dedicated
clock output, called CP or SCLK,
locked to the S-bus clock (see 4.11