MTC-20172-PC AMI Semiconductor, Inc., MTC-20172-PC Datasheet - Page 87

• Manufacturer Part Number: MTC-20172-PC
• Description: S Interface Circuit for ISDN (SIC)
• Manufacturer: AMI Semiconductor, Inc.

9.5.5 Static Characteristics Of Analog S-bus Outputs.
# Total impedance of series resistors,
9.6 Dynamic Characteristics.
Dynamic timing parameters are shown in Figures 9.1 to 9.4.
9.6.1 Master Clock
The timing parameters and signal thresholds are shown in Figure 9.1.
The master clock has a nominal period of 130.2 ns.
# Characteristics at the XTLO output
Table 9.6: Static Characteristics of the S-bus Outputs
Table 9.7: Dynamic Characteristics of the Master Clock
PARAMETERS
External Series Impedance
Output Impedance MARK
Output Impedance ZERO
Output Not powered (VDD=0V)
Output Current
differentially
Output Voltage on S-bus
(magnitude)
Output Voltage on S-bus
(magnitude)
Open Circuit Output Voltage
(magnitude)
XTLI
XTLI/O#
XTLI/O#
XTLI
XTLI
XTLI
XTLO #
XTLO #
XTLO #
PIN
transformer(2:1) + SIC drivers.
when the on chip free running
PARAMETER
Tr, Tf
Tp
Tw (high)
Tw (low)
Tr, Tf
Tw (high)
Tw (low)
frequency
freq error
Clock Width High
Clock Width High
DESCRIPTION
Rise and Fall Time
Clock Period
Clock Width Low
Rise and Fall Time
Clock Width Low
Master clock freq.
clock deviation
TEST COND.
SIC side
on S-bus
SIC side
SIC side
SIC side
(load imped.:)
S-bus 50Ω
Fig 5.3
S-bus 400Ω
Fig 5.4
SIC side
VDD = 5V
* External transformer (minimally 2.5
crystal oscillator is used. The load
on XTLO is maximum 30 pF.
k Ω ) in parallel on the S-bus.
77
2025
MIN
30 &
MIN
20 #
30 *
55.1
55.1
-100
675
675
135
90
90
65
20
20
± 7.5
(200)
1000
2100
7.68
TYP
TYP
750
100
133
140
70
& Guaranteed if S-bus differential
MTC-20172
Data Sheet & Reference Manual
Rev. 1.1 February 1997
signals are below 1.2 V peak.
± 13.3
MAX
2175
MAX
+100
1200
75.1
75.1
825
110
160
145
(0)
12
12
UNIT
UNIT
MHz
ppm
mA
mV
mV
mV
kΩ
kΩ
ns
ns
ns
ns
ns
ns
ns
%
%
%
Ω
Ω
Ω