MTC-20172-PC AMI Semiconductor, Inc., MTC-20172-PC Datasheet - Page 9

• Manufacturer Part Number: MTC-20172-PC
• Description: S Interface Circuit for ISDN (SIC)
• Manufacturer: AMI Semiconductor, Inc.

List of Figures
Fig. 1. Typical Application
Fig. 2.1 Timing in Normal mode
Fig. 2.2 Timing in V* Inverted mode
Fig. 2.3 Timing in V* Inverted Multiplexed mode
Fig. 2.4 Format of a V* GCI channel
Fig. 2.5 S0 Frame Format
Fig. 2.6 Point-to-point configuration
Fig. 2.7 Point-to-multipoint configuration
Fig. 2.8 Block Diagram
Fig. 2.9 Test loops
Fig. 2.10a Pinout, 22PDIL version
Fig. 2.10b Pinout, 28PLCC version
Fig. 3.1 22 pin DIP package and dimensions.
Fig. 3.2 28 pin PLCC square package and dimensions.
Fig. 3.3 22 pin DIP, signal names.
Fig. 3.4 28 pin PLCC, signal names.
Fig. 4.1 MTC-20172 SIC Applications
Fig. 4.2 Frame Structure GCI
Fig. 5.1 S Frame Structure
Fig. 5.2 S Coding with AMI
Fig. 5.3 Pulse Mask 50Ω
Fig. 5.4 Pulse Mask 400Ω
Fig. 5.5 GCI S-bus Phase Relation TE Mode, RDY & ECHO pin
Fig. 5.6 GCI S-bus Phase Relation NT/LT-S Mode, DE/CEB timing
Fig. 5.7 State Diagram of D-Channel Access Procedure
Fig. 6.1 Relation of clock, frame and data on the GCI bus
Fig. 6.1a Deactivation of the GCI interface
Fig. 6.2 SDL Diagram NT
Fig. 6.3 SDL Diagram LT-S
Fig. 6.4 SDL Diagram TE, LT-T
Fig. 6.5 Explanation of Notation of the SDL Diagrams
Fig. 6.6 SDL Diagram TE/LT-T, Unconditional states, Basic Mode
Fig. 6.7 Activation Sequence Outgoing Call
Fig. 6.8 Activation Sequence Incoming Call
Fig. 6.9 Deactivation Sequence
Fig. 6.10 SDL Diagram TE/LT-T, Unconditional states, Extended Mode
Fig. 6.11 SDL Diagram of the M-channel Receiver
Fig. 6.12 SDL Diagram of the M-channel Transmitter
Fig. 6.13 Examples of Received M-channel Messages
Fig. 6.14 Examples of Transmitted M-channel Messages
Fig. 9.1 Pulse Form of the 7.68 MHz Clock
Fig. 9.2 GCI Timing Parameters in TE
Fig. 9.3 GCI Timing Parameters in NT, LT-S and LT-T Mode
Fig. 12.1 Application circuitry for MTC20172 SIC
Fig. 12.2 Output pulse template for 50Ω
Fig. 12.3 Output pulse template for 400Ω
Fig. 12.4 Output impedance State_F1
Fig. 12.5 Output impedance State_F3
Fig. 12.6 Intput impedance State_F1
Fig. 12.7 Intput impedance State_F3
Fig. 13.1 MTC20172 SIC in NT mode with MTC2071 UIC
Fig. 13.2 Schematic of MTC20172 input and output Stage
IX
MTC-20172
Data Sheet & Reference Manual
Rev. 1.1 February 1997