MTC-20172-PC AMI Semiconductor, Inc., MTC-20172-PC Datasheet - Page 39

• Manufacturer Part Number: MTC-20172-PC
• Description: S Interface Circuit for ISDN (SIC)
• Manufacturer: AMI Semiconductor, Inc.

and Framing; Jitter
The transmitter data are sent at 192
kHz. The 192 kHz is derived from the
crystal frequency of 7 MHz, by
division by 40. The transmitter framing
is at 4 kHz. The timing is slaved to the
downlink clocks, the 4 kHz S-bus
frame is locked in phase to the
available downlink framing, see 5.5.
5.2.5.1 Transmitter Timing and
Framing at the NT/LT-S
With a DPLL, the 192 kHz clock is
locked to the GCI interface at the
NT/LT-S, by synchronizing the S-bus
frame with the GCI frame. The DPLL
locks the falling edge of the F/L frame
signal on the GCI frame signal, see
5.5. Jitter will be according to the
CCITT I.430 8.3.
5.2.5.2 Transmitter Timing and
Framing at the TE/LT-T
The 192 kHz is locked, with a DPLL, to
the downlink data. The transmit clock
frame reference is derived from the RX
F/L edge, as explained under
5.3.12.3. Jitter will be 2.5 % of a bit
period when receiving a clean input
signal. In the presence of noise and
jitter on the downlink data, the uplink
jitter will be larger. However, the TX
clock is derived with a DPLL which can
only adjust one 7 MHz period every
S-bus frame, which limits jitter
enhancement.
29
5.3 S-BUS Receiver:
The MTC-20172 SIC has an improved
ternary receiver. It is fully balanced, to
better reject longitudinal noise. It
handles higher attenuations on the S-
bus, with adaptive thresholds.
5.3.1 Transformer and Other
External Devices.
The receiver is connected to the S-bus
via a transformer with a 2:1 ratio,
similar to the transmitter. Using a
lower winding ratio reduces the useful
signal sensitivity. Moreover, the bit
detection thresholds will be not opti-
mal, especially for the short bus appli-
cations. The input transformer (toge-
ther with other filter elements) must
also reject longitudinal noise signals,
in order to fulfill symmetry require-
ments of CCITT's I.430 recommendat-
ion. Large common mode signals are
not tolerated by the input stage of the
MTC-20172 SIC. External series resis-
tors are needed for minimal impedan-
ce, see 5.3.3. Moreover, external
protection against foreign voltages is
needed (see appendix A).
5.3.2 Ternary S-bus Receiver
Polarity and Balanced
Operation
The ternary S-bus receiver is polarity
independent. It is fully balanced,
which means that it can be connected
to the balanced S-bus with a symmetri-
cal transformer, with a grounded
center tap at the S-bus side to better
reject longitudinal noise. The balan-
ced secondary is connected directly to
the MTC-20172 SIC with 2 series
resistors, as explained in 5.3.3.
The MTC-20172 SIC S-bus receiver is
backwards compatible with the unba-
lanced ones (e.g. MTC-2072 SIC).
MTC-20172
Data Sheet & Reference Manual
Rev. 1.1 February 1997
Analog Parts and
Synchronization