MTC-20172-PC AMI Semiconductor, Inc., MTC-20172-PC Datasheet - Page 28

• Manufacturer Part Number: MTC-20172-PC
• Description: S Interface Circuit for ISDN (SIC)
• Manufacturer: AMI Semiconductor, Inc.

4.10 MTC-20172
Activation of the MTC-20172 SIC
depends on the position and mode.
4.10.1 MTC-20172 SIC
Activation in NT Mode
Activation through the S-bus will be
seen by the signal detector. The MTC-
20172 SIC does not need crystal
input or GCI clock to activate the GCI
interface, which it does by
asynchronously pulling the data line
low. The master on the bus answers
with GCI clock and frame, followed
by commands via the C/I channel.
The bus master also delivers the crystal
frequency if it is generated externally
to MTC-20172 SIC, simultaneously
with GCI activation.
Activation through the GCI bus
consists of clock and frame delivery,
followed by commands via the C/I
channel. MTC-20172 SIC will activate
the S-bus transceiver according to the
commands, including the crystal
oscillator. If the master clock is
generated externally it must be
delivered to MTC-20172 SIC. Note
that the internal clock distribution to
the S-transceiver section is delayed for
2 ms (using the GCI frame clock), to
allow the crystal clock to stabilize.
SIC Activation
4.10.2 MTC-20172 SIC
Activation in TE Mode
Activation through the S-bus is
possible. The signal detector enables
the crystal, the GCI clock and frame is
activated, the receiver hunts for
synchronization, indications and
commands are exchanged via the C/I
channel and the MTC-20172 SIC
awaits further commands.
On activation through the GCI bus,
the controller pulls the data line low
(timing request). The MTC-20172 SIC
enables clock and frame, and C/I
codes are exchanged between the
MTC-20172 SIC and the controller.
One major difficulty exists: Once the
MTC-20172 SIC has acquired
synchronization on the downlink data,
the GCI frame must be adjusted to the
received frames. This is needed to
minimize transport delays of the B-
channels. There is an optimal fixed
relation between the received S-bus
frame and the GCI frame, see 5.5.2.
The locking of the GCI frame to the S-
bus frame causes a jump of the GCI
frame pulse. To limit the number of
phase jumps, the MTC-20172 SIC
only adjusts the free-running GCI pulse
when full synchronization on the S-bus
frames is acquired.
18
MTC-20172
Data Sheet & Reference Manual
Rev. 1.1 February 1997
4.10.3 MTC-20172 SIC
Activation in LT/S and LT/T
Modes
In this case, the GCI bus cannot be
shut down.
The GCI clock and frame run
continuously, but the MTC-20172 SIC
can be forced in a low power state
via the dedicated command. This
command deactivates the S-bus
transceiver. The crystal oscillator and
the internal clock distribution stay
enabled. The asynchronous signal
detector is the only active part in the
S-bus transceiver, the GCI part will
react on new C/I channel commands,
but runs no other activity internally.
4.10.4 Crystal Oscillator
Operation
In the LT-T/LT-S modes, the crystal
oscillator is permanently on, together
with the clock distribution.
In the NT mode, the crystal oscillator
is OFF during the power-down state,
and the crystal clock distribution at
wake-up is delayed after activation by
2 ms, by using the GCI frame clock.
In the TE-mode, the crystal will be shut
down in the power-down state, except
when the clock signals are requested
to stay active via the ENCK- pin, see
4.12.