MTC-20172-PC AMI Semiconductor, Inc., MTC-20172-PC Datasheet - Page 80

• Manufacturer Part Number: MTC-20172-PC
• Description: S Interface Circuit for ISDN (SIC)
• Manufacturer: AMI Semiconductor, Inc.

7.7.5 IN1 and IN2 Registers; READ Only; Address 4h and 5h
7.7.6 Performance Register; READ Only; Address 6h
The S1/Qbi bits are the received
multiframe channel bits, sampled
synchronously with the multiframing on
the S-bus.
The BUSY bit is also present here for
compatibility.
7.7.4 Output Register; WRITE and READ; Address 3h
(Note: The use of the AUXi pins as
generic inputs of outputs will collide
with their standard use as inputs.
EXAMPLE: one can use AUX1 as
extra output or input. However, the
pin AUX1 has the function DEX in LT-S
modes.
The signal on AUX1 will therefore
enable and disable the DE-bus, unless
DEX is disabled via CONF register.)
The bits represent the binary level of
the input pin. All value are sampled
asynchronously at the moment of the
PERF
OUT
Reset
AUXib1 AUXib0 : Configure the AUX4, AUX3 and AUX1 input/output pins
0
0
1
1
IN1
IN2
S1/Qb1
AUX4b1
0
AUX4
(TEST)
0
1
0
1
: The AUXi pin works as listed in 4.11 and 4.12
: The AUXi pin is tristate and usable as input.
: The AUXi pin is driven low.
: The AUXi pin is driven high.
S1/Qb2
AUX4b0
AUX3
SCLK
0
S1/Qb3
AUX3b1
XTR4
------
CONTENT message is assembled.
The BUSY bit is also present here for
compatibility.
Busy: READ only bit, present for
compatibility. Must be written at 0,
writing BUSY at 1 triggers test-modes.
Test: Must be written at 0, writing
TEST at 1 triggers test-modes.
SLIP: SET when a slip occurred in LT-
T mode, RESET after being read.
MFR: Indicates Multiframing
synchronization if at 1, in TE/LT-T.
BER: SET each time the BER pin goes
low, RESET after being read.
0
S1/Qb4
AUX3b0
AUX1
XTR3
0
70
BUSY
BUSY
BUSY
BUSY
0
MOD2
MTC-20172
Data Sheet & Reference Manual
Rev. 1.1 February 1997
XTR2
TEST
SLIP
0
AUX1b1
MOD1
XTR1
MFR
0
AUX1b0
MOD0
XTR0
BER
0