MTC-20172-PC AMI Semiconductor, Inc., MTC-20172-PC Datasheet - Page 78

• Manufacturer Part Number: MTC-20172-PC
• Description: S Interface Circuit for ISDN (SIC)
• Manufacturer: AMI Semiconductor, Inc.

These bits are sent continuously uplink
on the Q-channel, provided that
multiframing synchronization is found.
When the Q values changes via the
M-channel message, the new values
are put in the Q-channel
synchronously with the multiframe. (A
double buffer is used inside the MTC-
20172 SIC).
7.5.3 S/Q M-Channel Messages,
MTC-20172 SIC Multiframing
Disabled
If Multiframing is not enabled, the
MTC-20172 SIC ignores the content
of the incoming S/Q messages and
will not generate outgoing S/Q
messages. Multiframing enabling: see
5.9.2 and 7.7.3.
7.6 Internal Register
All internal register operations on the
M-channel are double byte messages.
Both READ and WRITE operations are
possible. After every operation, the M-
channel must go idle again.
Concatenation of double byte
messages could result in errors.
Messages which are aborted are
ignored. The MTC-20172 SIC
debounces the different bytes of the
message.
A WRITE operation is a one way mes-
sage, acknowledged only via the MR
bit, see 6.6. However, every register
can be read. A READ operation results
in an answer, delivering the content.
The READ operation causes the two
directions of the M-channel to be logi-
cally dependent! After the READ mes-
sage to the MTC-20172 SIC, the inco-
ming M-channel must return to IDLE.
The M-transceiver in the MTC-20172
SIC gives priority to the delivery of the
CONTENT and/or S/Q messages,
before it can handle the next incoming
(READ/WRITE or S/Q) message.
M-Channel Messages
7.6.1 Write Operation
For a Write operation, the double
byte messages is as follows:
No outgoing message in reaction to
the WRITE.
The second nibble is the address of
the internal register, limited from 1 to
6 in the MTC-20172 SIC. The write
addresses must differ from 0000,
otherwise the READ operation is
assumed.
7.6.2 Read Operation and
Content Message
For a Read operation, the double
byte messages is as follows:
The second nibble is all zero for an
internal READ operation. The fourth
nibble is the address of the register,
from 0 to 6.
The answer is the Content
message, two bytes as follows:
The second nibble is the address of
the internal register, with the BUSY bit
present in TE/LT-T modes.
The second byte contains the content
of the register, again with BUSY
present in the fifth position in TE/LT-T
modes.
To SIC byte 1:
To SIC byte 1:
From SIC byte 1: 1
byte 2:
byte 2:
byte 2:
68
1
1
X
CONTENT (MSB first to LSB last)
CONTENT (MSB first to LSB last)
0
0
X
0
0
0
0
X
0
0
X
0
MTC-20172
Data Sheet & Reference Manual
Rev. 1.1 February 1997
BUSY
X
0
X
ADR2
ADR2
ADR2
0
ADR1 ADR0
ADR1 ADR0
ADR1 ADR0
0
0