MTC-20172-PC AMI Semiconductor, Inc., MTC-20172-PC Datasheet - Page 41

• Manufacturer Part Number: MTC-20172-PC
• Description: S Interface Circuit for ISDN (SIC)
• Manufacturer: AMI Semiconductor, Inc.

5.3.9 Filtering:
The receiver filters the signal with a
continuous-time filter. This is a first
order filter, which is tuned to fix its 3
dB point at 192 kHz ±10 %. The
delay of this filter is taken into account
for the advance of the transmitter bit
clock (TE/LT-T), see 5.3.12.3, or for
the position of the fixed sampling
moment on the short passive bus
(NT/LT-S, fixed timing), see 5.3.10.
5.3.10 RX Frame Sync and Bit-
sampling In NT/LT-S Short Bus
Mode.
The bit-sampling moment is fixed, and
coupled with the TX bit clock, which in
turn is derived from the crystal clock,
and locked to the GCI frame. The RX
bit counters (giving the position of the
uplink bits in the frame) are also
locked to the downlink/TX bit counter.
Uplink data are 2 counts late.
The fixed bit-sampling moment is
advanced 5 periods of the 7 MHz
clock, before the edges of the SIC
transmit data stream. The advance is
needed to allow an advance of 7%
(or 3 periods) of the uplink data,
allowed according to the CCITT to be
sent by TE at zero distance, combined
with a 1 period jump of the downlink
data clock derived from the crystal.
This relationship is valid on the S-bus
itself. Inside the SIC, the actual bit
sampling is delayed to account for the
nominal delay of the external transfor-
mer, the internal filters and driver
delays. The total delay of the external
devices is estimated at 100 ns, the
internal delay is implementation
related (see also 5.3.9).
Moreover, the sampling can be
delayed extra by 5 periods of the 7
MHz clock via the XTR4 pin, and also
via internal register programming;
see 5.4.3.
The frame synchronization knows the
F position, and applies the rules of
5.1.9 (i.e. without oversampling).
The NT/LT-S in fixed bus mode can be
forced to loop the S-bus signals
internally. Then SIC applies adaptive
timing, to maximally test the device’s
functionality.
5.3.11 Frame Synchronization
Details in Adaptive Timing.
The general synchronization rules are
given under 5.1.8. They apply to
NT/LT/TE.
During synchronization, the device
oversamples the incoming bits with a
fixed threshold, which is at 33 % of the
nominal pulse height, with AGC active.
5.3.11.1 First Violation Detection
The oversampling is done at the 7
Mhz master clock, or a factor 40. A
simple voting technique is used to
detect a violation: The detector output
increments a counter as long as the
detected bits are marks of the same
polarity or zeros. When a polarity
change of the marks is seen, the coun-
ter is cleared. Whenever a sequence
of more than 50 oversampled marks
of the same polarity are seen, the
receiver decides that a violation came
in. The number 50 is not so large so
as to allow synchronization on signals
with flat edges.
After finding a single violation, the
oversampling looks for the mark-to-
zero and the subsequent zero-to-
opposite-mark transition, which it then
uses to estimate the actual F/L
crossing; see 5.3.12 below.
5.3.11.2 Violation Validation
During the hunt for frame synchroniza-
tion, the F/L transition forces the RX bit
sampling clock and bit counter to a
deterministic state, which is optimal;
see 5.3.12 below.
31
MTC-20172
Data Sheet & Reference Manual
Rev. 1.1 February 1997
The RX part now hunts for a next
violation. In fact, the next mark must
be a violation. This violation (polarity
should be opposite, but this is
ignored) must arrive before the
counter indicates 14 received bits. If
the second violation is found before
14 received bits, the F/L must be
validated for 2 more consecutive
frames.
In all following frames, the F/L
transition is oversampled to lock the
RX bit sampling clocks with DPLL
movements of 1 period of 7 MHz.
If the F/L validation is not correct
during the 2 subsequent frames,
MTC-20172 SIC restarts the hunt of
5.3.11.1.
5.3.12 RX Bit-Synchronization
in TE/LT-T and NT/LT-S Adaptive
Bus
Bit-Synchronization is done only by
detection of the F-L zero crossing. This
is optimal for short buses and extended
buses, where multiple signal sources
are present, each with an independent
bit timing. Only the F/L is a "stable"
combination of all electrical drivers on
the bus. For long point-to-point links,
the same technique is used.
Each time the bit counters indicate the
reception of F/L, the RX part
oversamples the transition at 7 MHz.
The F/L crossing is used for
several purposes:
1) It gives an immediate estimate of
2) It indicates how to correct the RX
the RX data optimal sampling
moment, after a first violation is
found, via oversampling.
(explained in 5.3.12.1)
192 kHz sampling clock each
frame by one 7 MHz period; (DPLL
action in adaptive RX sampling).
(explained in 5.3.12.2)