MTC-20172-PC AMI Semiconductor, Inc., MTC-20172-PC Datasheet - Page 17

• Manufacturer Part Number: MTC-20172-PC
• Description: S Interface Circuit for ISDN (SIC)
• Manufacturer: AMI Semiconductor, Inc.

The M control unit interprets and
responds to messages on the monitor
channel. Via this channel, access is
possible to the S/Q bits and
configuration registers. Observation of
some user-defined input pins is also
possible.
In order to reduce the power
consumption of the components
connected to the subscriber line, the
SIC may be switched to a power
down mode during idle periods. In NT
and TE modes, the internal clock
distribution and the oscillator are
turned off, and the power
consumption is less than 3 mW. The
component is automatically powered
up again during the line activation
procedure. The power consumption
when activated, with an applied DCLK
clock of 512 kHz is less than 50 mW
a) 22 PDIL : MTC-20172-PD
Fig. 2.9 : Pin Descriptions
MOD1
DOUT
DCLK
XTR2
XTR3
RSTB
VDD
SXN
DIN
DFR
SXP
1
2
3
4
5
6
7
8
9
10
11
20172
MTC
22
21
20
19
18
17
16
15
14
13
12
2.4 Test Modes
Two test loops may be closed in the
SIC, which depend on the selected
mode of operation. In both modes, all
three channels (B1, B2 and D) are
looped back as close as possible to
the So-interface.
Loop 2 (NT, LTS) is a transparent loop
(fig.2.9a) where the transmitted So-
frame is also switched on the S-bus.
Activation from the So-interface is not
possible.
Loop 3 (TE, LTT) is a non-transparent
loop (fig.2.9b) where the transmitted
So-frame is not switched on the S-bus
so as not to activate the NT/LTS.
Activation from the S-bus is possible,
and is indicated by a special code in
the C/I channel.
XTR0
MOD2
AUX2
SRP
VSS
XTR1
SRN
SCLK
MOD0
XTALI
XTALO
Summary
7
b) 28 PLCC : MTC-20172-PC
MOD1
DOUT
DCLK
XTR4
XTR2
DIN
DFR
4
MTC-20172
Data Sheet & Reference Manual
Rev. 1.1 February 1997
Both loops are initiated over the C/I-
channel and under control of a layer
2 component.
For further testing of the subscriber
line, two test signals can be
transmitted over the So-interface: A 96
kHz test sequence sending continuous
AMI marks, and a 2 kHz test
sequence sending single AMI marks.
Both test modes are under control of
the C/I channel and (in NT mode) by
means of device pins.
3 2 1 28
(Top view)
20172
MTC
AUX
XTLI
XTLO
VSS
SCLK
MOD0
XTR1