sc3200 Advanced Micro Devices, sc3200 Datasheet - Page 119
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sc3200
Manufacturer Part Number
sc3200
Description
Geode-tm Sc3200 Processor
Manufacturer
Advanced Micro Devices
Datasheet
1.SC3200.pdf
(447 pages)
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SuperI/O Module
5.4.2.5
ACCESS.bus ports 1 and 2 (ACB1 and ACB2) are identi-
cal. Each ACB is a two-wire synchronous serial interface
compatible with the ACCESS.bus physical layer. ACB1 and
ACB2 use a 24 MHz internal clock. Six runtime registers for
each
"ACCESS.bus Interface" on page 137.
AMD Geode™ SC3200 Processor Data Book
Index F0h
This register is reset by hardware to 00h.
Index
F0h
30h
60h
61h
70h
71h
74h
75h
Bit
7:3
1:0
2
ACCESS.bus
LDN 05h and 06h - ACCESS.bus Ports 1 and 2
Description
Reserved.
Internal Pull-Up Enable.
0: No internal pull-up resistors on AB1C/AB2C and AB1D/AB2D. (Default)
1: Internal pull-up resistors on AB1C/AB2C and AB1D/AB2D.
Reserved.
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
are
Configuration Register or Action
Activate. See also bit 0 of the SIOCF1 register
Base Address MSB register.
Base Address LSB register. Bits [2:0] (for A[2:0]) are RO, 000b.
Interrupt Number.
Interrupt Type. Bit 1 is R/W. Other bits are RO.
Report no DMA assignment.
Report no DMA assignment.
ACB1 and ACB2 Configuration register.
described
Table 5-14. ACB1 and ACB2 Configuration Register
Table 5-13. Relevant ACB1 and ACB2 Registers
ACB1 and ACB2 Configuration Register (R/W)
in
Section
5.7
ACB1 is designated as LDN 05h and ACB2 as LDN 06h.
Table 5-13 lists the configuration registers which affect the
ACCESS.bus ports. Only the last register (F0h) is
described here (Table 5-14). See Table 5-3 "Standard
Configuration Registers" on page 111 for descriptions of
the others.
Revision 5.1
Reset
Value
00h
00h
00h
00h
03h
04h
04h
00h
119
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