sc3200 Advanced Micro Devices, sc3200 Datasheet - Page 84

• Manufacturer Part Number: sc3200
• Description: Geode-tm Sc3200 Processor
• Manufacturer: Advanced Micro Devices

3.4.18
3.4.19
84
Signal Name
TCK
TDI
TDO
TMS
TRST#
Signal Name
GXCLK
TEST3
TEST2
TEST1
TEST0
GTEST
PLL6B
PLL5B
PLL2B
JTAG Interface Signals
Test and Measurement Interface Signals
Revision 5.1
EBGA
EBGA
AL16
AL16
AH6
AK4
AL4
AK5
B29
C28
D28
AL5
C28
B29
D28
AJ5
Ball No.
Ball No.
TEPBGA
TEPBGA
AG4
AH3
AG4
AH3
E31
E30
E29
V30
V30
F29
F28
AJ1
F30
AJ1
Type
Type
O
I
I
I
I
I/O
I/O
I/O
O
O
O
O
O
I
Description
JTAG Test Clock. This signal has an inter-
nal weak pull-up resistor.
JTAG Test Data Input. This signal has an
internal weak pull-up resistor.
JTAG Test Data Output
JTAG Test Mode Select. This signal has an
internal weak pull-up resistor.
JTAG Test Reset. This signal has an inter-
nal weak pull-up resistor.
For normal JTAG operation, this signal
should be active at power-up.
If the JTAG interface is not being used, this
signal can be tied low.
Description
GX Clock. This signal is for internal testing
only. For normal operation either program as
FP_VDD_ON or leave unconnected.
Internal Test Signal. This signal is used for
internal testing only. For normal operation
leave unconnected, unless programmed as
FP_VDD_ON.
Internal Test Signals. These signals are
used for internal testing only. For normal
operation, leave unconnected unless pro-
grammed as one of their muxed options.
Global Test. This signal is used for internal
testing only. For normal operation this signal
should be pulled down with 1.5 KΩ.
PLL6, PLL5 and PLL2 Bypass. These sig-
nals are used for internal testing only. For
normal operation leave unconnected.
AMD Geode™ SC3200 Processor Data Book
FP_VDD_ON+
FP_VDD_ON+
Signal Definitions
GXCLK
Mux
TEST3
TEST1
TEST2
TEST0
PLL5B
PLL6B
PLL2B
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Mux
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