sc3200 Advanced Micro Devices, sc3200 Datasheet - Page 44
![no-image](/images/manufacturer_photos/0/0/14/advanced_micro_devices_sml.jpg)
sc3200
Manufacturer Part Number
sc3200
Description
Geode-tm Sc3200 Processor
Manufacturer
Advanced Micro Devices
Datasheet
1.SC3200.pdf
(447 pages)
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44
Ball
No.
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
5, 2
5, 2
5,2
5,2
NC
NC
NC
Signal Name
AD23
A23
V
RD#
CLKSEL0
WR#
V
VSYNC
V
V
V
BUSY/WAIT#
TFTD3
F_C/BE1#
ACK#
TFTDE
FPCICLK
V
SLIN#/ASTRB#
TFTD16
F_IRDY#
INIT#
TFTD5
SMI_O
V
V
SS
SS
IO
SS
IO
IO
SS
SS
Table 3-4.
Revision 5.1
(PU/PD)
(PD
PWR
PWR
PWR
GND
GND
GND
GND
GND
I/O
I/O
---
---
---
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
100
)
481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
Buffer
IN
O
O
O
O
IN
Type
O
O
O
O
O
O
O
O
O
O
O
IN
IN
14/14
14/14
14/14
14/14
STRP
---
---
---
---
---
---
---
---
---
---
---
PCI
PCI
PCI
3/5
3/5
1/4
1/4
1/4
1/4
1/4
1/4
1/4
T
T
,
1
Power
Rail
V
V
V
V
V
V
V
V
---
---
---
---
---
---
---
---
---
---
---
IO
IO
IO
IO
IO
IO
IO
IO
Configuration
Cycle Multiplexed
---
---
Strap (See Table 3-
6 on page 58.)
---
---
---
---
---
---
---
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
---
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
---
---
---
3
3
3
3
3
3
3
3
3
3
3
3
= 0 and
= 1 and
= 0 and
= 0 and
= 1 and
= 0 and
= 0 and
= 1 and
= 0 and
= 0 and
= 1 and
= 0 and
Ball
No.
B25
B26
B27
B28
B29
B30
B31
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
5
5
Signal Name
V
NC
DPOS_PORT2
DNEG_PORT2
GPIO10
DSR2#
IDE_IORDY1
SDTEST1
V
V
AD26
D2
AD24
D0
V
AD25
D1
GNT0#
DID0
GNT1#
DID1
V
ROMCS#
BOOT16
GPIO19
INTC#
IOCHRDY
V
IRTX
SOUT3
V
V
V
SS
SS
IO
IO
IO
IO
SS
IO
SS
AMD Geode™ SC3200 Processor Data Book
(PU/PD)
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PD
(PD
(PD
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
---
O
O
O
O
O
O
I
I
I
I
I
I
I
22.5
22.5
22.5
22.5
22.5
22.5
22.5
100
100
100
)
)
)
)
)
)
)
)
)
)
Buffer
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
O
O
IN
IN
Type
IN
IN
O
O
O
O
O
O
O
O
O
IN
O
O
O
IN
O
O
STRP
STRP
STRP
---
---
USB
USB
---
---
---
---
---
---
---
---
USB
USB
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
TS1
TS1
TS
8/8
2/5
3/5
TS
3/5
8/8
8/8
TS
TS
,
,
,
,
,
,
,
,
,
,
1
Power
CUSB
CUSB
AV
AV
Rail
V
V
V
V
V
V
V
V
V
V
---
---
---
---
---
---
---
---
---
---
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
C-
C-
Signal Definitions
Configuration
---
---
---
---
PMR[18] = 0 and
PMR[8] = 0
PMR[18] = 1 and
PMR[8] = 0
PMR[18] = 0 and
PMR[8] = 1
PMR[18] = 1 and
PMR[8] = 1
---
---
Cycle Multiplexed
Cycle Multiplexed
---
Cycle Multiplexed
---
Strap (See Table 3-
6 on page 58.)
---
Strap (See Table 3-
6 on page 58.)
---
---
Strap (See Table 3-
6 on page 58.)
PMR[9] = 0 and
PMR[4] = 0
PMR[9] = 0 and
PMR[4] = 1
PMR[9] = 1 and
PMR[4] = 1
---
PMR[6] = 0
PMR[6] = 1
---
---
---
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