sc3200 Advanced Micro Devices, sc3200 Datasheet - Page 362

• Manufacturer Part Number: sc3200
• Description: Geode-tm Sc3200 Processor
• Manufacturer: Advanced Micro Devices

362
Offset 420h-423h
Offset 424h-427h
Offset 428h-43Bh
Offset 43Ch-43Fh
31:24
31:21
31:16
21:9
20:0
15:0
Bit
23
22
8
7
6
5
4
3
2
1
0
Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Description
Reserved. Must be set to 0.
ODD_TO (Odd Field Time Out). Indicates CGENTO0 (F4BAR0+Memory Offset 43Ch[15:0]) has expired. This bit can be
reset by writing 1 to it.
EVEN_TO (Even Field Time Out). Indicates CGENTO1 (F4BAR0+Memory Offset 43Ch[31:16]) has expired. This bit can
be reset by writing 1 to it.
Reserved.
Reserved. Set to 0.
Reserved. Set to 0.
Reserved. Set to 0.
Reserved. Set to 0.
GENLOCK_TOUT_EN (GenLock Timeout Enable).
0: Disable.
1: Enable timeout.
VIP_VSYNC_EDGE_SEL (VIP VSYNC Edge Select). Selects which edge of the VSYNC signal should be synchronized
with VIP.
0: Rising edge.
1: Falling edge.
GX1_VSYNC_EDGE_SEL (GX1 VSYNC Edge Select). Selects which edge of the VSYNC signal should be synchronized
with the GX1 module.
0: Rising edge.
1: Falling edge.
CT_GENLOCK_EN (Enable Continuous GenLock Function).
0: The continuous GenLock function is disabled.
1: Enable locking (i.e., synchronization) of the GX1 VSYNC with the VIP VSYNC on every VSYNC (i.e., continuous lock-
Note:
Reserved. Set to 0.
Reserved.
GENLOCK_DEL (GenLock Delay). Indicates the delay (in 27 MHz clocks) between the VIP VSYNC and the GX1 module’s
Display Controller VSYNC.
CGENTO1 (Even Field Continuous GenLock Timeout).
CGENTO0 (Odd Field Continuous GenLock Timeout).
ing).
If bit 0 (SG_GENLOCK_EN) = 1, it overrides the value of this bit.
Revision 5.1
Continuous GenLock Timeout Register (R/W)
GenLock Delay Register (R/W)
GenLock Register (R/W)
Reserved
Video Processor Module - Video Processor Registers - Function 4
AMD Geode™ SC3200 Processor Data Book
Reset Value: 1FFF1FFFh
Reset Value: 00000000h
Reset Value: 00000000h