sc3200 Advanced Micro Devices, sc3200 Datasheet - Page 313

• Manufacturer Part Number: sc3200
• Description: Geode-tm Sc3200 Processor
• Manufacturer: Advanced Micro Devices

Core Logic Module - ISA Legacy Register Space
6.4.7
The ISA Legacy registers reside in the ISA I/O address
space in the address range from 000h to FFFh and are
accessed through typical input/output instructions (i.e.,
CPU direct R/W) with the designated I/O port address and
8-bit data.
The bit formats for the ISA Legacy I/O Registers plus two
chipset-specific configuration registers used for interrupt
mapping in the Core Logic module are given in this section.
The ISA Legacy registers are separated into the following
DMA Channel Control Registers, see Table 6-43
AMD Geode™ SC3200 Processor Data Book
I/O Port 000h
Written as two successive bytes, byte 0, 1.
I/O Port 001h
Written as two successive bytes, byte 0, 1.
I/O Port 002h
Written as two successive bytes, byte 0, 1.
I/O Port 003h
Written as two successive bytes, byte 0, 1.
I/O Port 004h
Written as two successive bytes, byte 0, 1.
I/O Port 005h
Written as two successive bytes, byte 0, 1.
I/O Port 006h
Written as two successive bytes, byte 0, 1.
I/O Port 007h
Written as two successive bytes, byte 0, 1.
I/O Port 008h (R/W)
Read
Bit
7
6
5
4
3
ISA Legacy Register Space
Description
Channel 3 Request. Indicates if a request is pending.
0: No.
1: Yes.
Channel 2 Request. Indicates if a request is pending.
0: No.
1: Yes.
Channel 1 Request. Indicates if a request is pending.
0: No.
1: Yes.
Channel 0 Request. Indicates if a request is pending.
0: No.
1: Yes.
Channel 3 Terminal Count. Indicates if TC was reached.
0: No.
1: Yes.
Table 6-43. DMA Channel Control Registers
DMA Channel 0 Transfer Count Register (R/W)
DMA Channel 1 Transfer Count Register (R/W)
DMA Channel 2 Transfer Count Register (R/W)
DMA Channel 3 Transfer Count Register (R/W)
DMA Channel 0 Address Register (R/W)
DMA Channel 1 Address Register (R/W)
DMA Channel 2 Address Register (R/W)
DMA Channel 3 Address Register (R/W)
DMA Status Register, Channels 3:0
• DMA Page Registers, see Table 6-44
• Programmable Interval Timer Registers, see Table 6-45
• Programmable Interrupt Controller Registers, see Table
• Keyboard Controller Registers, see Table 6-47
• Real-Time Clock Registers, see Table 6-48
• Miscellaneous Registers, see Table 6-49 (includes
6-46
4D0h and 4D1h Interrupt Edge/Level Select Registers)
Revision 5.1
313