sc3200 Advanced Micro Devices, sc3200 Datasheet - Page 321

• Manufacturer Part Number: sc3200
• Description: Geode-tm Sc3200 Processor
• Manufacturer: Advanced Micro Devices

Core Logic Module - ISA Legacy Register Space
AMD Geode™ SC3200 Processor Data Book
I/O Port 020h / 0A0h
I/O Port 021h / 0A1h
I/O Port 021h / 0A1h
Master PIC ICW3
Slave PIC ICW3
I/O Port 021h / 0A1h
I/O Port 021h / 0A1h (R/W)
Bit
7:5
7:3
2:0
7:0
7:0
7:5
3:2
4
3
2
1
0
4
1
0
7
6
5
4
3
Description
Reserved. Must be set to 0.
Reserved. Must be set to 1.
Trigger Mode.
0: Edge.
1: Level.
Vector Address Interval
0: 8 byte intervals.
1: 4 byte intervals.
Reserved. Must be set to 0 (cascade mode).
Reserved. Must be set to 1 (ICW4 must be programmed).
A[7:3]. Address lines [7:3] for base vector for interrupt controller.
Reserved. Must be set to 0.
Cascade IRQ. Must be 04h.
Slave ID. Must be 02h.
Reserved. Must be set to 0.
Special Fully Nested Mode.
0: Disable.
1: Enable.
Reserved. Must be set to 0.
Auto EOI.
0: Normal EOI.
1: Auto EOI.
Reserved. Must be set to 1 (8086/8088 mode).
IRQ7 / IRQ15 Mask.
0: Not Masked.
1: Mask.
IRQ6 / IRQ14 Mask.
0: Not Masked.
1: Mask.
IRQ5 / IRQ13 Mask.
0: Not Masked.
1: Mask.
IRQ4 / IRQ12 Mask.
0: Not Masked.
1: Mask.
IRQ3 / IRQ11 Mask.
0: Not Masked.
1: Mask.
Table 6-46. Programmable Interrupt Controller Registers
Master / Slave PIC ICW2 (after ICW1 is written) (WO)
Master / Slave PIC ICW3 (after ICW2 is written) (WO)
Master / Slave PIC ICW4 (after ICW3 is written) (WO)
(except immediately after ICW1 is written)
Master / Slave PIC ICW1 (WO)
Master / Slave PIC OCW1
Revision 5.1
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