sc3200 Advanced Micro Devices, sc3200 Datasheet - Page 61

• Manufacturer Part Number: sc3200
• Description: Geode-tm Sc3200 Processor
• Manufacturer: Advanced Micro Devices

Signal Definitions
1.
2.
3.
AMD Geode™ SC3200 Processor Data Book
EBGA
AL15
AL12
AL16
AJ13
AB2
AA3
AA1
AB1
H30
W3
W2
W1
H4
U3
T1
Y3
Y1
V1
V2
V3
U1
T3
T4
H3
H2
J4
The combination of PMR[21] = 1 and PMR[2] = 0 is undefined and should not be used.
The combination of PMR[9] = 1 and PMR[4] = 0 is undefined and should not be used.
These TFT outputs are reset to 0 by POR# if the TFT_PRSNT strap is pulled high or PMR[10] = 0. This relates to signals TFTD[17:0],
TFTDE, TFTDCK.
Ball No.
Ball No.
Ball No.
Ball No.
Ball No.
Ball No.
TEPBGA
V31
B18
D22
B17
D21
B21
C21
A21
D20
C20
C18
C19
A20
A18
D17
C17
B20
A22
A10
D10
N31
N30
AJ8
V30
C9
A9
GPIO16
GPIO17
GPIO20
AB1D
GPIO11
GXCLK
GPIO19
AFD#/DSTRB#
GPIO1
AB1C
STB#/WRITE#
BUSY/WAIT#
/ASTRB#
Signal
SLIN#
ERR#
ACK#
SLCT
INIT#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE
Table 3-8. Three-Signal/Group Multiplexing (Continued)
Internal Test
Parallel Port
Default
GPIO
GPIO
GPIO
AB1
PMR[0] = 0 and
FPCI_MON = 0
PMR[9] = 0 and
PMR[4] = 0
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23] = 0 and
PMR[5] = 0
PMR[23] = 0 and
PMR[7] = 0
PMR[23] = 0 and
PMR[13] = 0
PMR[23] = 0
PMR[23] = 0
PMR[18] = 0 and
PMR[8] = 0
PMR[23] = 0 and
PMR[29] = 0
Configuration
PC_BEEP
INTC#
TFTDE
TFTD2
TFTD3
TFTD4
TFTD5
TFTD6
TFTD7
TFTD8
TFTD9
TFTD10
TFTD11
TFTD1
TFTD13
TFTD14
TFTD15
TFTD16
TFTD17
IOCS0#
DOCCS#
IOCS1#
GPIO20
GPIO1
RI2#
TEST3
Signal
Internal Test
Alternate1
Sub-ISA
UART2
GPIO
TFT
PCI
PMR[0] = 1 = 0 and
FPCI_MON = 0
PMR[4] = 1
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23] = 0 and
PMR[5] = 1
PMR[23] = 0 and
PMR[7] = 1
PMR[23] = 0 and
PMR[13] = 1
PMR[7] = 0
PMR[23] = 1 and
PMR[13] = 0
PMR[8] = 0
PMR[9] = 0 and
PMR[23] = 1 and
PMR[23] = 1 and
PMR[18] = 1 and
PMR[23] = 0 and
PMR[29] = 1
Configuration
2
3
Revision 5.1
F_DEVSEL
IOCHRDY
FPCI_CLK
INTR_O
F_C/BE1#
F_C/BE0#
SMI_O
F_AD0
F_AD1
F_AD2
F_AD3
F_AD4
F_AD5
F_AD6
F_AD7
F_C/BE2#
F_C/BE3#
F_IRDY
F_FRAME#
TFTDCK
TFTD0
TFTD12
DOCCS#
IOCS1#
IRQ15
FP_VDD_ON
Signal
FPCI Monitoring
Alternate2
Sub-ISA
Sub-ISA
TFT
IDE2
TFT
FPCI_MON = 1
PMR[9] = 1 and
PMR[4] = 1
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23] = 1
PMR[23] = 1
PMR[23] = 1
PMR[23] = 1 and
PMR[7] = 1
PMR[23] = 1 and
PMR[13] = 1
PMR[18] = 0 and
PMR[8] = 1
PMR[23] = 1
Configuration
3
61