sc3200 Advanced Micro Devices, sc3200 Datasheet - Page 17

• Manufacturer Part Number: sc3200
• Description: Geode-tm Sc3200 Processor
• Manufacturer: Advanced Micro Devices

Architecture Overview
As illustrated in Figure 1-1 on page 13, the SC3200 pro-
cessor contains the following modules in one integrated
device:
• GX1 Module:
• Video Processor Module:
• Core Logic Module:
• SuperI/O Module:
2.1
The GX1 processor (silicon revision 8.1.1) is the central
module of the SC3200. For detailed information regarding
the GX1 module, refer to the AMD Geode™ GX1 Proces-
sor Data Book and the AMD Geode™ GX1 Processor Sili-
con Revision 8.1.1 Specification Update documents.
AMD Geode™ SC3200 Processor Data Book
— Combines advanced CPU performance with MMX
— A low-power TFT support module with a video input
— Includes PC/AT functionality, an IDE interface, a
— Includes two Serial Ports, an Infrared (IR) Port, a
support, fully accelerated 2D graphics, a 64-bit
synchronous DRAM (SDRAM) interface and a PCI
bus controller. Integrates GX1 silicon revision 8.1.1.
port, and a hardware video accelerator for scaling,
filtering and color space conversion.
Universal Serial Bus (USB) interface, ACPI v1.0
compliant power management, and an audio codec
interface.
Parallel Port, two ACCESS.bus interfaces, and a
Real-Time Clock (RTC).
GX1 Module
2.0Architecture Overview
The SC3200 processor’s device ID is contained in the GX1
module. Software can detect the revision by reading the
DIR0 and DIR1 Configuration registers (see Configuration
registers in the AMD Geode™ GX1 Processor Data Book).
The AMD Geode™ SC3200 Specification Update docu-
ment contains the specific values.
2.1.1
The GX1 module is connected to external SDRAM devices.
For more information see Section 3.4.2 "Memory Interface
Signals" on page 65, and the “Memory Controller” chapter
in the AMD Geode™ GX1 Processor Data Book.
There are some differences in the SC3200 processor’s
memory controller and the stand-alone GX1 processor’s
memory controller:
1)
2)
Table 2-1 summarizes the 32-bit registers contained in the
SC3200 processor’s memory controller. Table 2-2 gives
detailed register/bit formats.
There is drive strength/slew control in the SC3200 that
is not in the GX1. The bits that control this function are
in the MC_MEM_CNTRL1 and MC_MEM_CNTRL2
registers. In the GX1 processor, these bits are marked
as reserved.
The SC3200 supports two banks of memory. The GX1
supports four banks of memory. In addition, the
SC3200 supports a maximum of eight devices and the
GX1 supports up to 32 devices. With this difference,
the MC_BANK_CFG register is different.
Memory Controller
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