SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 20

• Manufacturer Part Number: SST34WA3283
• Description: 32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
• Manufacturer: Silicon Storage Technology, Inc.

Advance Information
prevents a collision. When a collision occurs, WAIT asserts
until the refresh is complete. The Read continues normally
once the refresh is complete. During asynchronous Read
and Write, ignore asserted WAIT.
Using the PSRAM in burst mode with fixed latency
(BCR[14] = 1), does not require WAIT monitoring. WAIT
will indicate when valid data is available at the start of the
burst and the end of the row. However, when WAIT is not
monitored, the controller must stop burst access at the row
boundaries.
LBS#/UBS#
Byte-wide data transfers are accomplished by the LBS#
and UBS# enable signals. During Read, enabled bytes are
driven to the A/DQs and disabled bytes A/DQs are put into
High-Z state. Disabled bytes are not transferred to the RAM
during a Write, and their values are unchanged. During
asynchronous Write, data is latched on the rising edge of
the first occurrence of either BES#, WE#, or LBS#/UBS#.
The data bus will not receive or transmit data when both
LBS# and UBS# are disabled (High) during an operation;
however, as long as BES# remains Low, the device
remains in active mode.
Standby Mode
After the completion of a Read or Write, or when the
address and control inputs are static for an extended
period, the PSRAM enters Standby mode when BES# is
driven High. In Standby, power consumption are reduced to
a level necessary to perform DRAM refresh. Standby
continues until a change in address or PSRAM control
input occurs.
©2007 Silicon Storage Technology, Inc.
FIGURE 4: WAIT Configuration
Other
Device
Other
Device
WAIT
WAIT
Processor
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
READY
External
Pull-Up/
Pull-Down
Resistor
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
WAIT
Pseudo
1358 F52.0
SRAM
Burst
20
Temperature Compensated Refresh
An on-chip temperature sensor automatically regulates the
refresh rate according to the operating temperature. The
Temperature compensated refresh (TCR) continually
adjusts the refresh rate and ensures that sufficient
refreshes occur at various temperatures.
Deep Power-Down
If the system does not require the storage provided by the
PSRAM, Deep Power-down (DPD) disables all refresh
related activities; however, DPD will corrupt any stored
data. After re-enabling the refresh activity, the device
requires 150 µs to initialize before normal operations
resume. During this time, the current consumption is
higher than during specified standby levels, but
considerably
specification. To enable DPD, Write to the RCR using
CRES or the software access sequence. DPD starts
when BES# is driven High; and is disabled the next
time BES# is driven Low and remains for at least 10ns.
lower
than
the
S71358-01-000
active
current
11/07