SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 7

• Manufacturer Part Number: SST34WA3283
• Description: 32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
• Manufacturer: Silicon Storage Technology, Inc.

32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
Writing Commands
The SST34WA32A3/32A4/3283/3284 accept address and
data information in the form of program commands. To
write a command, the system needs to drive BEF#, and
WE# to V
of AVD# while keeping OE# at V
the rising edge of WE# while keeping OE# at V
Word-Program Operation
The SST34WA32A3/32A4/3283/3284 are programmed on
a word-by-word basis. Before programming, erase the
sector to be programmed.
A Program operation is accomplished in three phases.
First, the Software Data Protection is initiated using the
three-word load sequence. Next, the word address and
word data are loaded. Finally, the internal Program
operation initiates after the rising edge of the fourth WE#.
The Program operation completes within 12 µs.
The
programming acceleration mode for faster programming.
Once the device enters the programming acceleration
mode, only two write cycles are required to program a
word, instead of the four cycles required in the standard
program command sequence.
During the Program operation, the only valid reads within
the bank being programmed are status reads (DQ
Polling and DQ
during an internal Program operation are ignored.
When the Program Operation is complete, the bank will
return to Read Array Mode. For Program operation timing
diagram and flowchart, see Figure 13 and Figure 47.
Programming Acceleration Operation
The programming acceleration makes programing faster
than using a standard program command sequence
because it reduces the standard four-cycle process to two
cycles. Two unlock cycles initiates the programming
acceleration command sequence which is followed by a
third write cycle containing 20H as the programming
acceleration command. The chip enters the programming
acceleration mode. To program in this mode, a two-cycle
programming acceleration program command sequence is
all that is required. The first cycle contains the
programming acceleration command, A0h; the second
cycle contains the program address and data. Likewise,
additional data is programmed. The initial two unlock cycles
required in the standard program command sequence is
eliminated. This reduces the total programming time. See
Table 20 for programming acceleration command
sequence requirements.
The system issues a two-cycle programming acceleration
reset command sequence to exit the programming
©2007 Silicon Storage Technology, Inc.
SST34WA32A3/32A4/3283/3284
IL
. The addresses are latched on the rising edge
2
/DQ
6
Toggle Bits). Any commands issued
IH
, and data is latched on
features
IH .
7
Data#
an
7
acceleration mode and return to the read mode. The first
cycle contains the data 90h, and the second cycle contains
the data 00h.
Eight-Word Program
An Eight Word Program command is provided for fast data
programming. At room temperature and normal
command is only enabled when the ACC pin is at
Supervoltage VH (11.4V to 12V). The Eight Word Program
Operation is initiated with the A0H command and then the
host provides eight consecutive data words. The Eight
Word program is an Asynchronous operation and the CLK
signal is ignored. The system drives BEF# low to
the Initial address is latched on the rising edge of the first
AVD# pulse while keeping OE# high. Data is latched on the
rising edge of each WE# pulse while keeping OE# high.
See Figure 15 for AC timings. The Initial address A
be 8-words boundary aligned (A
the part will force the boundary alignment. Each
subsequent WE# pulse will automatically increment the
address of one word from A
issue 8 data words to be programmed when in Eight Word
Program Mode.
Standby Mode
The SST34WA32A3/32A4/3283/3284 flash memory enter
the Standby mode when both the BEF# and RST# inputs
are held at
access time (T
data.
Auto Low Power Mode
The flash memory of these devices have the Auto Lower
Power mode which puts it in a near standby mode. In
Asynchronous read mode, this happens when addresses
remain stable within T
with a valid Read operation. This reduces the flash active
Read current to 3 µA, typically.
While BEF# is low, the device exits Auto Low Power mode
with any address transition or control signal transition used
to initiate another flash Read cycle, with no access time
penalty. While in Auto Low Power mode, output data is
latched and always available to the system.
In synchronous read mode, after the AVD# falling edge, the
flash memory automatically enters the Auto Low Power
mode when there is no active CLK edge within T
60ns. The flash memory exits Auto Low Power mode with
an active CLK edge.
V
DD
CE
) for read access before it is ready to read
± 0.2 V. The device requires standard
ACC
+ 60 ns after data is accessed
INI
0
to A
= A
Advance Information
INI + 7
1
= A
S71358-01-000
. The user must
2
= 0), otherwise
V
INI
V
DD
IL
ACC
must
, the
and
11/07
+