SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 27

• Manufacturer Part Number: SST34WA3283
• Description: 32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
• Manufacturer: Silicon Storage Technology, Inc.

32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
TABLE 15: Pin Descriptions
©2007 Silicon Storage Technology, Inc.
Symbol
A
A/DQ
BEF#
OE#
WE#
RST#
RY/BY#
CLK
AVD#
WP#
A
V
V
V
V
NC
RFU
CRES
BES#
LBS#
UBS#
20
CC
DDQ
DD
SS
SSQ
-A
15
16
-A/DQ
0
Name
Address Inputs
Multiplexed Address/Data Sixteen least-significant bit Addresses are multiplexed with Data Input/output.
Flash Memory Enable
Output Enable
Write Enable
Hardware Reset
Ready Output
Clock
Address Valid Input
Write Protect
Vpp Power Supply
I/O Power Supply
Power Supply
Ground
Ground for I/O Power
Supply
No Connection
Reserve for future use
Configuration Register
Enable (PSRAM)
PSRAM Memory Enable
Lower Byte Control
(PSRAM)
Upper Byte Control
(PSRAM)
To provide memory addresses.
To activate the flash memory bank when BEF# is low.
To gate the data output buffers
RY/BY# signal when the Flash memory is selected. WAIT signal when the
Activate the PSRAM when low.
Functions
The outputs are in tri-state when OE# or BEF# is high.
To control the Write operations
To reset and return the flash memory to Read mode
PSRAM is selected.
To increment the internal address counter (after the initial output delay) when the
part is in Burst Mode. CLK is not required in asynchronous mode.
To indicate to the device that a valid Address is present on the Address Bus
To protect and unprotect top or bottom 8 KWord (4 outermost sectors) of the
flash memory bank from Erase or Program operation.
Supervoltage VH (11.4V to 12V) input to enable eight word programming of the
flash memory bank. When at V
conditions.
To provide power for Input/Output Buffers.
To provide 1.7-1.95V power supply voltage. V
together in the application circuit.
V
Unconnected pins
Don't make any connection on these pins.
When CRE is high, Write operations load the Refresh configuration register, Bus
configuration register or Device ID register.
Gates the data on the lower byte of the data bus during a write operation or Data
gated from the lower part of the selected address during a read operation.
Gates the data on the upper byte of the data bus during a write operation or Data
gated from the upper part of the selected address during a read operation.
SS
and V
SSQ
need to be shorted together in the application circuit.
27
IL
locks all sectors. Should be at V
DD
and V
DDQ
Advance Information
need to be shorted
S71358-01-000
IH
for all other
T15.1 1358
11/07