SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 62

• Manufacturer Part Number: SST34WA3283
• Description: 32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
• Manufacturer: Silicon Storage Technology, Inc.

Advance Information
©2007 Silicon Storage Technology, Inc.
FIGURE 34: PSRAM Burst Write Followed by Burst Read
A/DQ
Notes: 1. Non-default BCR settings for burst WRITE followed by burst READ: Fixed latency; latency code two
LBS#/UBS#
A
15
max
–A/DQ
2. A refresh opportunity must be provided every T
3. Only fixed latency requires T
AVD#
BES#
WAIT
–A
WE#
OE#
CLK
(three clocks); WAIT active LOW; WAIT asserted during delay.
following two conditions: a) clocked BES# HIGH, or b) BES# HIGH for longer than 15ns. BES# can stay LOW
between burst READ and burst WRITE operations, but BES# must not remain LOW longer than T
See burst interrupt diagrams for cases where BES# stays LOW between bursts.
16
0
VIH
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
High-Z
Address
Address
Valid
Valid
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
T
T
T
T
SPS
SPS
BESS
SPS
T
High-Z
T
T
T
CLK
HDS
HDS
SPS
CAVDS
D[0] D[1] D[2] D[3]
.
T
SPS
T
T
HDS
CAVDS
T
HDS
T
HDS
3
BEPS
62
T
SPS
Note 2
T
. A refresh opportunity is satisfied by either of the
HDS
Address
Valid
VOH
VOL
T
T
BACCS
BPHS
T
T
T
High-Z
SPS
SPS
BESS
T
HDS
Output
Valid
T
OES
Output
Valid
T
BDHS
Output
T
Valid
OHZS
Output
Valid
BEPS
1358 F35.0
S71358-01-000
High-Z
.
11/07