SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 5

• Manufacturer Part Number: SST34WA3283
• Description: 32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
• Manufacturer: Silicon Storage Technology, Inc.

32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
8-16-32-Words Linear Burst Mode without Wrap-
Around
The
supports a synchronous read operation with a Linear Burst
mode that does not wrap around. A fixed number of words
predefined as 8-, 16-, or 32-words are read from
consecutive addresses starting with the initial word, which
is written to the device. Once the fixed number of words are
read completely, the Burst Read operation stops and the
RY/BY# output goes low. There is no group limitation as
there is with Linear Burst with Wrap-Around. See Table 3
for group definitions.
An example of an 8-word linear Burst mode without Wrap-
Around is as follows: for an 8-word length Burst Read, if the
starting address written to the device is 39h, the burst
sequence would be 39-3A-3B-3C-3D-3E-3F-40h, and the
read operation will be terminated at 40h. In a similar
fashion, the 16-word and 32-word modes begin their burst
sequence on the starting address written to the device, and
Continuously Read to the predefined word length, of 16 or
32 words.
The operation is similar to the Continuous Burst, but will
stop the operation at fixed word length. If the device
crosses the first 32-word address boundary during burst
read, a latency may occur before data appears for the next
address and RY/BY# is pulsing low. If the burst read start
address is 8-word boundary aligned (A0 = A1 = A2 = 0),
the latency does not occur. If the host system crosses the
bank boundary, the device will react in the same manner as
in the Continuous Burst.
Continuous Linear Burst Mode
The flash memory of SST34WA32A3/32A4/3283/3284
supports a synchronous read operation with a continuous,
sequential linear Burst mode read. When in this mode, the
Addresses are automatically incremented linearly with
every successive clock active edge. If the device reaches
the Highest Memory Location Address (FFFFFH), it will
continue the continuous, sequential linear Burst read
operation by wrapping around to Address 00000H. The
Burst operation will continue sequentially until another
address is latched via the AVD# pin, until BEF# is driven to
V
When an address is latched via AVD# pin with active edge
of CLK, a new burst read will start with a new initial
address.
If the continuous, sequential linear burst read sequence
crosses a bank boundary into a bank that is performing a
Programming or Erasing operation, the device will provide
status information. Once the system has completed the
status read operation, or the device has completed the
Program/Erase Operation, the system is allowed to start a
new burst read operation. In this case a new address
needs to be latched via the AVD# pin.
©2007 Silicon Storage Technology, Inc.
IH
, or until RST# is driven to
SST34WA32A3/32A4/3283/3284
V
IL
.
flash
memory
5
In synchronous, continuous, sequential, linear read array, a
latency in output data may occur when a burst sequence
crosses the first 32-word address boundary. If the burst
read start address is 8-word boundary aligned (A
A
address is mis-aligned to an 8-word boundary, the delay
occurs once per burst-mode read sequence. The RY/BY#
signal will indicate this delay to the system.
Burst Register
The flash memory of SST34WA32A3/32A4/3283/3284
defaults to Asynchronous Read on power-up. However, it
can be configured to operate in a Synchronous Read
Mode with continuous, sequential linear burst operation
and linear burst operation of 8-, 16-, 32- words length with
wrap-around.
The Burst Register is used to configure the type of read bus
access the flash memory will perform by setting the desired
Mode of Burst (continuous or wrap-around) and the
number of wait states for the initial word access time
(T
The user can set the Burst Register with the Set Burst
Register Command. The Burst Register will retain its
information until it is reset via the RST# pin or after Power-
Up.
The Set Burst Register Command is initiated by executing
a three-cycle command sequence. On the last bus cycle,
Data is C0H, address bits A
bits A
Table 4.
Upon power-up or hardware reset using the RST# pin, the
device will be in the default state. The Burst Register
cannot be changed if the device is Programming, Erasing,
or if it is in Sector Lock/Unlock mode.
2
IACC
= 0), the delay does not occur. If the burst read start
17
).
–A
12
set the code to be latched, as shown in
11
–A
0
are 555H, and address
Advance Information
S71358-01-000
0
= A
11/07
1
=