SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 22

• Manufacturer Part Number: SST34WA3283
• Description: 32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
• Manufacturer: Silicon Storage Technology, Inc.

Advance Information
PSRAM Configuration Registers
The
PSRAM
Register (BCR) and Refresh Configuration Register (RCR).
Register Read/Program using CRES
When the control register enable (CRES) input is High,
access
synchronous mode. When CRES is Low, access the
PSRAM array with either a Read or Write operation.
Values are written to the configuration registers using
addresses A
UBS# are Don’t Care and values are latched on the rising
edge of either AVD#, BES#, or WE#, depending on which
occurs first. In SST34WA32A3/32A4, when A
10b, BCR is accessed; when A
accessed
SST34WA3283/3284, when A
accessed; when A18-A17 are 01b, BCR is accessed and
A
During reads, register bits 15 to 0 are output on A/DQ
and
SST34WA32A3/32A4, and A
©2007 Silicon Storage Technology, Inc.
16
FIGURE 6: Set Configuration Register - Software Method
must be set to 0.
address
SST34WA32A3/32A4/3283/3284
the
configuration
max
and
A/DQ
registers
1. To program the BCR or the RCR on last bus write cycle, A/DQ
2. Configuration Data In: Only the Bus Configuration Register(BCR) and the Refresh Configuration Register
3. The control signals BES#, OE#, WE#, LBS# and UBS#, must be toggled as shown in the above figure.
- A
LBS#/UBS#
inputs
A
15
respectively.
(RCR) can be modified.
0
A
max
. During synchronous Write, LBS# and
–A/DQ
17
BES#
AVD#
–A
WE#
-A
OE#
16
16
other than
0
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
registers:
in
must be set to 0. In
18
either
18
19
- A
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
-A
Max Address
Max Address
- A
17
17
Bus
18
for SST34WA3283/
asynchronous
are 00b, RCR is
Read Cycle
A
are 00b, RCR is
19
features
Configuration
19
- A
- A
18
18
Max Address
Max Address
two
15-0
are
for
or
Read Cycle
22
3284, are Don’t Care. On completion of a Read or Write
operation on a register, immediately execute Read on the
memory array. A
Read or Program using CRES.
Register Read/Program using Software Method
Do not use the software method to disable or enable the
Deep Power-down mode (bit 4 of the RCR). To Read and
Program the BCR and RCR, first issue a Read
Configuration Register sequence and then issue a Set
Configuration Register sequence, while CRES is Don’t
Care. Both the Read Configuration Register sequence and
the Set Configuration sequence require four read and write
cycles which are performed in asynchronous mode.
Two bus read cycles followed by one write cycle to the Max
address—a unique address location—indicates whether
the next operation is a read or write. During the third cycle,
write 000h to access RCR and 001h to access BCR, in the
next cycle. The configuration register is written to, or read
from, during the fourth cycle.
Software
asynchronous write and read timings.
15
Max Address
Max Address
–A/DQ
Read/Program
Write Cycle
0
must be set to ‘0001h’ and ‘0000’
17
- A
Note1
16
must be Low during a register
Max Address
Max Address
timings
Write Cycle
1358 F03.0
are
Note2
S71358-01-000
identical
11/07
to