SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 9

• Manufacturer Part Number: SST34WA3283
• Description: 32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
• Manufacturer: Silicon Storage Technology, Inc.

32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
.
TABLE 5: Erase-Suspend and Concurrent Banks State
Chip-Erase Operation
The SST34WA32A3/32A4/3283/3284 provides a Chip-
Erase operation which allows the user to erase the entire
flash memory array to the ‘1’ state. This is a quick way to
erase the entire flash memory. To initiate the Chip-Erase
execute a six-word command sequence with the Chip-
Erase command, 10H, at address 555H in the last word
sequence. The Erase operation begins with the rising edge
of the sixth WE#. During the Erase operation, the only valid
reads are Toggle Bit or Data# Polling. See Table 20 for the
command sequence, Figure 14 for timing diagram, and
Figure 51 for the flowchart. Any commands issued during
the Chip-Erase operation are ignored, including the Erase-
Suspend Command. If WP# pin is held to
more blocks are locked, the Chip Erase Operation is
disabled.
Write Operation Status Detection
The
system flash Write cycle time by providing two software
means to detect the completion of a Program Write cycle or
an Erase Write cycle. The software detection includes two
status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The
End-of- Write detection mode, which is enabled after the
rising edge of WE#, initiates the internal Program or Erase
operation. The actual completion of the nonvolatile write is
asynchronous with the system; therefore, either a Data#
Polling (DQ7), or Toggle Bit (DQ6) Read may be
simultaneous with the completion of the Write cycle. If this
occurs, the system will get an erroneous result. For
example, valid data may appear to conflict with either DQ7
or DQ6. In order to prevent spurious rejection when an
erroneous result occurs, the software routine must include
a loop to read the accessed location an additional time. If
both Reads indicate the completion, then the Write cycle
has completed.
©2007 Silicon Storage Technology, Inc.
Current Operation in
One Bank
Sector/Block-Erase-Suspend
Sector/Block-Erase-Suspend
Sector/Block-Erase-Suspend
Sector/Block-Erase-Suspend
Sector/Block-Erase-Suspend
Sector/Block-Erase-Suspend
SST34WA32A3/32A4/3283/3284
Possible Operation in The Same Bank
Read any other Sector/Block within the same Bank
Read any other Sector/Block within the same Bank
Program any other Sector/Block within the same
Bank
Program any other Sector/Block within the same
Bank
No Operation
No Operation
optimizes
V
IL
, or one or
the
9
Ready (RY/BY#)
The RY/BY# pin is a dedicated status output that indicates
valid output data on A/DQ15–A/DQ0 during synchronous
burst reads. When RY/BY# is asserted (RY/BY# = V
the output data is valid and can be read. When RY/BY# is
de-asserted (RY/BY# = V
BY# is re-asserted before expecting the next word of data.
Two conditions cause the RY/BY# output to be low: during
the initial access while in burst mode, and when the device
is set to Continuous Burst Mode and the address crosses
the first 32 word boundary.
In asynchronous, non-burst mode, the RY/BY# pin does
not indicate valid or invalid output data. Instead, RY/BY# =
V
V
Data# Polling (DQ7)
When the SST34WA32A3/32A4/3283/3284 is in the
internal Program operation, any attempt to read DQ7 will
produce the complement of the true data. Once the
Program operation is completed, DQ7 will produce true
data. During internal Erase operation, any attempt to read
DQ7 will produce a ‘0’. Once the internal Erase operation is
completed, DQ7 will produce a ‘1’. The Data# Polling is
valid after the rising edge of fourth WE# pulse for Program
operation. For Sector/ Block or Chip-Erase, the Data#
Polling is valid after the rising edge of sixth WE# pulse. See
Figure 16 for Data# Polling timing diagram and Figure 48
for a flowchart.
OH
IH
.
when BEF# =
V
Possible Operation in Any Other
Concurrent Bank
No Operation
Program any Sector/Block
No Operation
Read any Sector/Block
Read any Sector/Block
Program any Sector/Block
IL
, and RY/BY# is Hi-Z when BEF# =
OL
), the system will wait until RY/
Advance Information
S71358-01-000
T5.0 1358
OH
11/07
),