SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 64

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SST34WA3283

Manufacturer Part Number
SST34WA3283
Description
32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
Manufacturer
Silicon Storage Technology, Inc.
Datasheet
Advance Information
©2007 Silicon Storage Technology, Inc.
FIGURE 36: PSRAM Burst Write Interrupted by Burst Write or Read - Fixed Latency
A/DQ
2nd Cycle WRITE
Notes: 1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in
2nd Cycle WRITE
2nd Cycle WRITE
LBS#/UBS#
A
15
max
–A/DQ
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
2. Burst interrupt shown on first allowable clock (i.e., after first data word written).
3. BES# can stay LOW between burst operations, but BES# must not remain LOW longer
BES#
AVD#
WAIT
–A
WE#
CLK
OE#
fixed latency mode: Fixed latency; latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay.
than T
A/DQ
16
0
2nd Cycle READ
2nd Cycle READ
2nd Cycle READ
LBS#/UBS#
VIH
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
15
BEPS
–A/DQ
High-Z
T
AAHS
.
OE#
Address
Address
Valid
Valid
0
T
T
T
T
SPS
SPS
BESS
T
SPS
T
High-Z
T
T
HDS
CLK
HDS
CAVDS
T
T
BEWS
SPS
D[0]
T
SPS
Address
T
64
Valid
BEPS
VOH
VOL
T
T
BACCS
WRITE Burst interrupted with new WRITE or
READ. See Note 2.
OES
T
T
SPS
SPS
High-Z
(Note 3)
T
T
HDS
T
HDS
T
T
SPS
CWS
AAHS
Output
Valid
D[0]
Output
Valid
D[1] D[2] D[3]
T
T
BDHS
HDS
T
Output
HDS
Valid
Output
Valid
1358 F37.0
T
High-Z
HDS
T
OHZS
S71358-01-000
11/07

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