s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 174

• Manufacturer Part Number: s908ey8ad4cfjer
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (SPI) Module
15.5.2 Transmission Format When CPHA = 0
Figure 15-4
replacement for data sheet parametric information. Two waveforms are shown for SCK: one for CPOL = 0
and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the
serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI
signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives
to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the
master must be high or must be reconfigured as general-purpose I/O not affecting the SPI (see
Mode Fault
slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to
start the transmission. The SS pin must be toggled high and then low again between each byte
transmitted.
15.5.3 Transmission Format When CPHA = 1
Figure 15-5
replacement for data sheet parametric information. Two waveforms are shown for SCK: one for CPOL = 0
and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the
serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI
signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives
to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the
master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See
Mode Fault
Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low
between transmissions. This format may be preferable in systems having only one master and only one
slave driving the MISO data line.
174
CAPTURE STROBE
FOR REFERENCE
FROM MASTER
SCK CPOL = 0
SCK CPOL = 1
SCK CYCLE #
FROM SLAVE
SS TO SLAVE
Error). When CPHA = 0, the first SPSCK edge is the MSB capture strobe. Therefore, the
Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge.
shows an SPI transmission in which CPHA (SPCR) is 0. The figure should not be used as a
shows an SPI transmission in which CPHA (SPCR) is 1. The figure should not be used as a
MOSI
MISO
MSB
Figure 15-4. Transmission Format (CPHA = 0)
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
MSB
1
BIT 6
BIT 6
2
BIT 5
BIT 5
3
BIT 4
BIT 4
4
BIT 3
BIT 3
5
BIT 2
BIT 2
6
BIT 1
BIT 1
7
Freescale Semiconductor
LSB
LSB
8
15.6.2
15.6.2