s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 274

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s908ey8ad4cfjer

Manufacturer Part Number
s908ey8ad4cfjer
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Revision History
Changes from Rev 0.2 published on 1 August 2001 to Rev 0.3 published
274
Input/Output (I/O) Ports
Configuration Registers
Preliminary Electrical
Preliminary Electrical
Low-Voltage Inhibit
Timebase Module
Timer Interface A
Timer Interface B
Timer Interface A
Timer Interface B
Communications
Analog-to-Digital
Converter (ADC)
Converter (ADC)
Enhanced Serial
Analog-to-Digital
Interface (ESCI)
(TIMA) Module
(TIMB) Module
(TIMA) Module
(TIMB) Module
Specifications
Specifications
Memory Map
(CONFIG1 &
(LVI) Module
CONFIG2)
on 6 September 2001
Section
Section
Module
Module
Module
(TBM)
Page (in Rev 0.4)
Page (in Rev 0.3)
243 and 244
382 and 384
382 and 384
382 and 384
384 and 386
388 and 392
279 – 301
303 – 326
361 – 376
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
210
238
345
354
355
366
386
391
150
152
188
189
190
191
280
304
336
337
338
345
347
391
50
Note added regarding length of break character when followed by an idle.
Prescale bits renamed
ACLK = 0 description changed
Several updates for clarification
Several updates for clarification
Reserved register bits redefined as unimplemented
Table 20-1 updated to show all unused combinations
Left Justified Mode description corrected
Reserved register bits redefined as unimplemented
Port B description updated
Changes to:
Hi-Z leakage current
Input current
Monitor mode entry voltage
External clock frequency of operation
FLASH page erase time
$001E TMBCLKSEL and SSBPUENB bits added
$001E TMBCLKSEL and SSBPUENB bits added
Corrections to Table 8-1: PTB6 to PTC4 and PTB7 to PTC3
Figure 12-1 updated, digital filter removed
False reset protection text updated
Table 12-1 updated
References to digital filter removed
External clock input removed from features
External clock input removed from features
Divide-by-128 replaced by divide-by-1024
Figure 19-1 updated
Note added after Table 19-1
PTC and Cx removed from Figure 20-1
ADCR changed to ADCLK
Control Timing specifications added
SPI characteristics added
FLASH
read bus clock frequency changed to 8
Description of change
Description of change
MHz
Freescale Semiconductor

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