s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 264

• Manufacturer Part Number: s908ey8ad4cfjer
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Glossary
opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be connected to the
operand — Data on which an operation is performed. Usually a statement consists of an operator and
oscillator — A circuit that produces a constant frequency square wave that is used by the computer as
OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that cannot be
overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted. In a
PC — See “program counter (PC).”
peripheral — A circuit not under direct CPU control.
phase-locked loop (PLL) — A oscillator circuit in which the frequency of the oscillator is synchronized
PLL — See "phase-locked loop (PLL)."
pointer — Pointer register. An index register is sometimes called a pointer register because its contents
polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage
polling — Periodically reading a status bit to monitor the condition of a peripheral device.
port — A set of wires for communicating with off-chip devices.
prescaler — A circuit that generates an output signal related to the input signal by a fractional scale factor
program — A set of computer instructions that cause a computer to perform a desired operation or
program counter (PC) — A 16-bit register in the CPU08. The PC register holds the address of the next
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power supply to provide the logic 1 output voltage.
an operand. For example, the operator may be an add instruction, and the operand may be the
quantity to be added.
a timing and sequencing reference.
reprogrammed.
system that uses odd parity, every byte is expected to have an odd number of logic 1s. In an even
parity system, every byte should have an even number of logic 1s. In the transmitter, a parity
generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even
for even parity. A parity checker in the receiver counts the number of logic 1s in each byte. The parity
checker generates an error signal if it finds a byte with an incorrect number of logic 1s.
to a reference signal.
are used in the calculation of the address of an operand, and therefore points to the operand.
levels, V
such as 1/2, 1/8, 1/10 etc.
operations.
instruction or operand that the CPU will use.
DD
and V
SS
.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor