s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 199

• Manufacturer Part Number: s908ey8ad4cfjer
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

PWM function, and TIMA channel 1 status and control register (TASC1) is unused. While the MS0B bit is
set, the channel 1 pin, PTD1/TACH1, is available as a general-purpose I/O pin.
17.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use this initialization
procedure:
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMA
channel 0 registers (TACH0H–TACH0L) initially control the buffered PWM output. TIMA status control
register 0 (TASC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority
over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMA overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. See
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1. In the TIMA status and control register (TASC):
2. In the TIMA counter modulo registers (TAMODH–TAMODL), write the value for the required PWM
3. In the TIMA channel x registers (TACHxH–TACHxL), write the value for the required pulse width.
4. In TIMA channel x status and control register (TASCx):
5. In the TIMA status control register (TASC), clear the TIMA stop bit, TSTOP.
period.
a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP.
b. Reset the TIMA counter prescaler by setting the TIMA reset bit, TRST.
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level
or PWM signals) to the mode select bits, MSxB–MSxA. See
select bits, ELSxB–ELSxA. The output action on compare must force the output to the
complement of the pulse width level. See
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
17.8.4 TIMA Channel Status and Control
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
NOTE
NOTE
Table
Registers.
17-2.
Table
17-2.
Functional Description
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