s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 185

• Manufacturer Part Number: s908ey8ad4cfjer
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

SPRIE — SPI Receiver Interrupt Enable Bit
SPMSTR — SPI Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPWOM — SPI Wired-OR Mode Bit
Freescale Semiconductor
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
Figure 15-4
identical CPOL bits. Reset clears the CPOL bit.
This read/write bit controls the timing relationship between the serial clock and SPI data. (See
Figure 15-4
identical CPHA bits. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1
between bytes. (See
When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once
the transmission begins, no new data is allowed into the shift register from the data register. Therefore,
the slave data register must be loaded with the desired transmit data before the falling edge of SS. Any
data written after the falling edge is stored in the data register and transferred to the shift register at
the current transmission.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission.
The same applies when SS is high for a slave. The MISO pin is held in a high-impedance state, and
the incoming SPSCK is ignored. In certain cases, it may also cause the MODF flag to be set. (See
15.6.2 Mode Fault
machine.
This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins
become open-drain outputs.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
1 = Master mode
0 = Slave mode
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
Address:
and
and
Reset:
Read:
Write:
Figure
Figure
Error). A logic 1 on the SS pin does not in any way affect the state of the SPI state
$000D
SPRIE
Bit 7
Figure
R
0
15-5.) To transmit data between SPI modules, the SPI modules must have
15-5.) To transmit data between SPI modules, the SPI modules must have
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Figure 15-12. SPI Control Register (SPCR)
= Reserved
15-11). Reset sets the CPHA bit.
R
6
0
SPMSTR
5
1
CPOL
4
0
CPHA
3
1
SPWOM
2
0
SPE
1
0
SPTIE
Bit 0
0
I/O Registers
185