mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 11

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

BURST TERMINATE
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated
as shown in the Operation section of this data sheet.
AUTO REFRESH
of the SDRAM and is analogous to CAS#-BEFORE-
RAS# (CBR) REFRESH in conventional DRAMs. This
command is nonpersistent, so it must be issued each
time a refresh
mand is generated by an internal refresh controller.
This means that the address lines are not used to
generate the refresh address, and are “Don’t Care”.
REFRESH cycles every 64ms (
row is refreshed. Distributed refresh would be achieved
by providing an AUTO REFRESH command once ev-
ery 31.25µs. Burst refresh could be accomplished by
issuing 2,048 AUTO REFRESH commands consecu-
tively at the minimum cycle rate of
would be doubled. Thus, 2,048 AUTO-REFRESH com-
mands distributed every 15.625µs would allow the 1
Meg x 16 SDRAM to have a 4K refresh if required. Of
the three types of refreshs options, utilizing the 2,048
cycles every 64ms (31.25µs per refresh) provides the
maximum power savings.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
The BURST TERMINATE command is used to trun-
AUTO REFRESH is used during normal operation
is required.
The addressing during an AUTO REFRESH com-
The 1 Meg x 16 SDRAM requires 2,048 AUTO
To provide a 4K refresh scheme, the refresh rate
t
REF) to ensure that each
t
RC.
11
SELF REFRESH
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking. The
SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
Once the SELF REFRESH command is registered, all the
inputs to the SDRAM become “Don’t Care,” with the
exception of CKE, which must remain LOW.
provides its own internal clocking, causing it to per-
form its own auto refresh cycles. The SDRAM must
remain in self refresh mode for a minimum period
equal to
an indefinite period beyond that.
sequence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing con-
straints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
t
any internal refresh in progress.
commands may be issued every 15.625µs or less as both
SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
XSR, because time is required for the completion of
The SELF REFRESH command can be used to retain
Once self refresh mode is engaged, the SDRAM
The procedure for exiting self refresh requires a
Upon exiting self refresh mode, AUTO REFRESH
t
RAS, and may remain in self refresh mode for
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16Mb: x16
IT SDRAM
©1999, Micron Technology, Inc.